Overview

This IP (*2) can be applied to our evaluation kit EASYSS10 Box. By applying it, the customer can immediately use the EASYSS10 Box as an ST2022-6/8 SDI/IP Gateway evaluation machine without modifying it.

Features

◇ IP transmission of SDI signals conforming to SMPTE ST 2022-6 standard
- Enables SDI-IP transmission without the need for a ST 2059-1/2 PTP Grandmaster
- Transmitter SDI clock recovered on receiver and SDI output. Suppression of rapid SDI output phase fluctuations caused by network jitter (Clock Recovery function)

◇ IP transmission of SDI signals conforming to SMPTE ST 2022-8 standard
- SDI-IP transmission synchronized to PTP Grandmaster according to ST 2059-1/2

◇ Compliant with SMPTE ST 2022-7 standard
- Redundant transmission with Hitless Protection using 2 network interface ports

◇ Simultaneous transmission of up to 6 SDI streams
- Transmission method (ST 2022-6/ST 2022-8) can be specified for each stream
- Automatic recognition of input/output SDI format and mixed transmission of SDI with different Resolution and Frame Rate

◇ Provide API with provided software (SDK)
- FPGA registers, PTP, IGMP, etc. can be controlled via API. Customers can focus on software development of the upper layer.
- Includes reference applications (Web GUI, CUI). It is possible to understand API specifications with documents and source code.

◇ In addition to normal IGMP control, an IGMP control function that prevents excess network usage bandwidth is installed (Bandwidth Exceed Protection option)

specification

◇ SMPTE® Profile
-ST 2022-6
-ST 2022-7
-ST 2022-8
- ST 2110-10
- ST 2059-1/2

◇ NMOS Profile
- IS-04 *Planned
- IS-05 *Planned

◇ SDI format
-Resolution
1280x720p (HD-SDI), 1920x1080i (HD-SDI), 1920x1080p (3G-SDI)
-Frame Rate
50Hz, 59.94Hz, 60Hz

◇ Ethernet Interface
- 10GbE x 2
- 25 GbE x 2 *Planned

◇ IGMP
- IGMP version 2, version 3

Application example

◇ ST 2022-6 SDI/IP Gateway application example

◇ ST 2022-8 SDI/IP Gateway application example

corresponding device

◇ Intel® Arria® 10 SoCs
◇ Intel® Arria® 10 GX + NXP® i.MX7D *Planned
◇ Intel® Stratix® 10 SoC *Planned

Device usage resources

◇ Device : 10AS066K3F40E2SG
◇ Device : 10AS066K3F40E2SG
◇ Logic utilization (in ALMs) : 122,098 / 251,680 (49%)
◇ Total registers : 244890
◇ Total block memory bits: 7,082,272 / 43,642,880 (16%)
◇ Total RAM Blocks : 714 / 2,131 (34%)
◇ Total DSP Blocks : 5 / 1,687 ( < 1 % )
◇ Total HSSI RX channels: 9 / 36 (25%)
◇ Total HSSI TX channels: 9 / 36 (25%)
◇ Total PLLs : 52/80 (65%)
◇ DDR
- Memory used: 4Gb (256Mx16 MT40A256M16GE-083E) x 4
- Memory clock : 933.33MHz

The above values are approximate circuit scale values and devices used based on our implementation example. It may vary depending on the customer's system configuration.

Block Diagram

Release Status / Schedule

◇ Now on sale

Offerings

Inquiry