Points to be aware of when developing products using PCI Express

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PCI Express is an interface used in the development of many products. In the design process, it is common to check the device datasheet and determine specifications such as "how many lanes to use" and "which generation to use" before proceeding with the design. On the other hand, while decisions related to PCI Express are made during the design process, they are often treated as implicit assumptions.

This article does not aim to explain the PCI Express standard itself. Rather, it will summarize points that, if overlooked during the design phase of product development using PCI Express, can have repercussions later on.

What is PCI Express?

What kind of interface is PCI Express?

PCI Express (PCIe) is a high-speed serial interface standard for connecting CPUs and SoCs to peripheral devices. It communicates using "lanes," which are bundles of multiple differential signals, and the available bandwidth is determined by the number of lanes used and the generation (Gen). PCI Express defines configurations such as x1, x4, x8, and x16, and the configuration is selected according to the product's performance requirements. Furthermore, PCI Express is not merely a signal routing standard, but is defined as a system-oriented interface that includes mechanisms for initialization, link establishment, and error control.

The basic concepts of PCI Express, such as lanes and bandwidth, are explained in the following article, so please refer to it if you are interested.

The absolute basics you need to know before diving into PCI Express design

How was PCI Express designed?

When using PCI Express in product development, designers typically first check the device datasheet and reference configuration to understand specifications such as "which generations are supported" and "how many lanes are available at maximum." Based on this, they then determine the number of lanes to use and the configuration according to product requirements and constraints on the SoC/FPGA side.

On the other hand, PCI Express is a common standard, and the same name and notation are used across various products and devices. Therefore, it is sometimes treated in the design process as follows:

The number of lanes and the generation are determined based on the device specifications and reference configuration.
Once the number of lanes or generation is decided, it is often treated as a premise for subsequent circuit design and layout considerations.
During the design process, opportunities to re-examine the structure itself tend to be limited.

As a result, PCI Express-specific properties and constraints are sometimes treated alongside other design conditions without being specifically addressed in the design decision-making process.

What happens if you design with the assumption that PCI Express is "the same because it's a standard"?

PCI Express is defined as a common standard, and all devices use the same name, generation, and lane configuration. Therefore, in the early stages of design, considerations may proceed under the assumption that "if they are the same generation and have the same number of lanes, their basic behavior will be the same." PCI Express is a standard that prioritizes compatibility, and is designed to allow different devices to connect to each other if certain conditions are met. On the other hand, the behavior of PCI Express is also significantly affected by the actual system configuration and implementation conditions.
For example, even if they are the same generation and have the same number of lanes,
• Types of devices to be connected
- Implementation and internal configuration of the SoC/CPU
- Circuit board wiring, power supply, and clock conditions
These factors can change the design considerations and constraints. If the design proceeds under the assumption that "the standards are the same," these differences may go unnoticed during the design process. This is because the number of lanes and the generation are already determined, making it difficult to see a reason to reconsider them. As a result, PCI Express-specific properties are treated on the same level as other design conditions, and the design proceeds accordingly.
It's possible that the effects only become apparent in later stages of the process.

Five points to be aware of when designing with PCI Express that could cause problems if you don't know them.

PCI Express is defined as a common standard, and it is used to configure systems by combining SoCs, CPUs, and peripheral devices. On the other hand, PCI Express is not an interface that is completed solely by signal wiring,
The design process involves everything from device implementation and board design to startup conditions, and even the influence of settings and software. Therefore, whether or not you are aware of "where the points to pay attention to are" from the beginning of the design process can greatly affect how easy it is to check and troubleshoot in later stages.

This section outlines key points to consider in the early stages of design when using PCI Express.

1. What is the scope of my design?

How far does your design scope extend? When designing with PCI Express, it's often not possible to complete the work within a single area of responsibility.
For example, even with the same PCI Express connection,
• PCI Express functionality on the SoC/CPU side
- Implementation on the connected device side
• Wiring and component placement on the circuit board
• Configuration and software involvement
Several factors are involved. Therefore, if you don't have a clear understanding of what your (or your team's) design scope is at the beginning of the design process, it can become difficult to know "what to check" when the impact becomes apparent in later stages. What's important to remember here is that PCI Express is an interface that is not confined to a single design element. Simply sharing this premise will make it easier to organize the subsequent considerations and separation of issues.

2. Establish links with power, reset, and clock.

PCI Express is not an interface where communication automatically begins if the signal wiring is done correctly. For a link to be established, certain conditions must be met in a specific sequence, including power-on, reset release, and clock supply. Once these conditions are met, PCI Express enters a communication state through a procedure called Link Initialization and Training (LTSSM). While the focus tends to be on the number of lanes and wiring configuration in the early stages of design, in reality, if these "startup prerequisites" are not met, the link will not be established even if the wiring is correct.

3. Gen/Lane Count is not just about performance.

In PCI Express-based designs, the question of "which generation (Gen) to use" and "how many lanes to use" are often determined primarily by the required performance (bandwidth).
for example,
- Increasing Gen will make it faster
Increasing the number of lanes will provide more bandwidth.
Such organization is a natural approach in the early stages of design. On the other hand, the Gen and number of lanes directly affect not only performance but also implementation requirements and design difficulty.
Even though they are both PCI Express,
• The demands on signal quality become stricter with each new generation.
The more lanes there are, the more constraints there are on wiring and component placement.
As such, the conditions that affect the entire board design and configuration change. Therefore, if you decide on a generation (Gen) or a number of lanes to be on the safe side, constraints on the implementation side may become apparent in later stages of the process. What you need to keep in mind here is that the generation and number of lanes are not only performance indicators, but also design conditions themselves.

4. Involvement of software or settings

PCI Express is not a hardware-only interface. After the link is established, configuration and software involvement are involved before it becomes truly "usable." While it's easy to perceive PCI Express as simply a "physically connected interface" in the early stages of design, in reality,
Device settings
- Recognition by the OS and drivers
- Results of initialization and enumeration
These factors ultimately determine how it looks and how it behaves. Therefore, even if the link itself is established,
- Not recognized in the expected configuration
- The number of lanes and speed do not meet expectations.
This is a situation that can occur. What's important to keep in mind here is that in designs using PCI Express, the hardware configuration and the results of the settings and software are inseparable. Having this premise in mind in the early stages of design makes it easier to clarify "what is hardware-related and what is settings and software-related" when checking the status in later stages.

5. Not knowing "where to look" when you're in trouble.

PCI Express is an interface that enters a communication state after going through procedures such as link establishment and training. Therefore, when something doesn't work as expected, what's important is not "trying to guess the cause," but rather having an observation point that allows you to understand which stage it's stuck at. However, if you proceed with designing while treating PCI Express as "the same because it's a standard," you'll run into problems.
• Startup conditions (power, reset, clock)
• Physical transmission conditions (wiring and mounting)
- Configuration and software-side results (recognition/enumeration)
It can easily become unclear where to start checking. What's important to remember here is that PCI Express has a state transition (LTSSM) until the link is established, and there's a way of thinking about troubleshooting by looking at "how far the process has progressed" in terms of state. The same reasoning applies to organizing things into layers, which makes it easier to figure out where to look for trouble.

Summary

PCI Express is a common standard, but what matters in design is not whether you "know the standard," but rather the assumptions you make while designing. Differences in the timing of when things like wiring, startup conditions, generation, number of lanes, settings, and software are considered during the design process can have repercussions later on.

I hope this article will serve as a starting point for thinking about "where and what is important" when designing with PCI Express.