Part # Device Name |
10SG050 |
10SG065 |
10SG085 |
10SG110 |
10SG165 |
10SG210 |
10SG250 |
10SG280 |
10SG450 |
10SG550 |
|
---|---|---|---|---|---|---|---|---|---|---|---|
Stratix 10 products |
GX500 |
GX650 |
GX850 |
GX1100 |
GX1650 |
GX2100 |
GX2500 |
GX2800 |
GX4500 |
GX5500 |
|
Equivalent number of LEs |
484,000 |
646,000 |
841,000 |
1,092,000 |
1,624,000 |
2,005,000 |
2,422,000 |
2,753,000 |
4,463,000 |
5,510,000 |
|
Number of adaptive logic modules |
164,160 |
218,880 |
284,960 |
370,080 |
550,540 |
679,680 |
821,150 |
933,120 |
1,512,820 |
1,867,680 |
|
Number of ALM registers |
656,640 |
875,520 |
1,139,840 |
1,480,320 |
2,202,160 |
2,718,720 |
3,284,600 |
3,732,480 |
6,051,280 |
7,470,720 |
|
Number of Hyper-Registers |
Distribute millions of Hyper-Registers across a monolithic FPGA fabric |
||||||||||
Number of Synthesizable Clock Trees |
Thousands of Synthesizable Clock Trees |
||||||||||
GXT full duplex |
16 |
16 |
32 |
32 |
64 |
64 |
96 |
96 |
48 |
48 |
|
GX full-duplex transceiver count |
8 |
8 |
16 |
16 |
32 |
32 |
48 |
48 |
24 |
24 |
|
Maximum number of transceivers |
24 |
24 |
48 |
48 |
96 |
96 |
144 |
144 |
72 |
72 |
|
M20K |
2,196 |
2,583 |
3,477 |
4,401 |
5,851 |
6,501 |
9,963 |
11,721 |
7,033 |
7,033 |
|
M20K memory |
43 |
50 |
68 |
86 |
114 |
127 |
195 |
229 |
137 |
137 |
|
MLAB memory |
3 |
3 |
4 |
6 |
8 |
11 |
13 |
15 |
23 |
29 |
|
Variable precision DSP |
1,152 |
1,440 |
2,016 |
2,520 |
3,145 |
3,744 |
5,011 |
5,760 |
1,980 |
1,980 |
|
18x19 |
2,304 |
2,880 |
4,032 |
5,040 |
6,290 |
7,488 |
10,022 |
11,520 |
3,960 |
3,960 |
|
Fixed-point performance (TMACS) |
4.6 |
5.8 |
8.1 |
10.1 |
12.6 |
15.0 |
20.0 |
23.0 |
7.9 |
7.9 |
|
Single precision floating point performance |
1.8 |
2.3 |
3.2 |
4.0 |
5.0 |
6.0 |
8.0 |
9.2 |
3.2 |
3.2 |
|
Maximum user I/O |
488 |
488 |
736 |
736 |
704 |
704 |
1160 |
1160 |
1640 |
1640 |
|
PCIe® |
1 |
1 |
2 |
2 |
4 |
4 |
6 |
6 |
3 |
3 |
|
Number of secure device managers |
AES-256/SHA-256 bitsstream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side channel attack protection |
||||||||||
Number of hard processor systems |
Quad-core 64 bit ARM® Cortex®-A53 up to 1.5 GHz with 32 KB I/D cache, NEONTM coprocessor, 1 MB L2 cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers , USB 2.0 x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general-purpose timers x7, watchdog timer x4 |
Notes:
*1. LE numbers are for comparison between Intel® devices and are conservative numbers for competing FPGA products.
*2. Fixed-point performance (TMACS) assumes the use of a pre-adder.
*3. Floating point performance is single precision conforming to IEEE 754.
*4. Quad-core ARM® Cortex®-A53 hard processor system is supported only by Stratix® 10 SX SoC devices.