How to lower Idc

(a) Maintaining a logic state in which DC power does not flow
3rd time column, the pull-up/down buffer keeps the logic state in which no DC current flows for a long time.

(b) avoid signal conflicts
If the signals of the bi-directional buffer conflict (the L signal and the H signal collide), Vcc and GND are connected, so a large amount of power is consumed.
Avoid conflicts or keep conflict times short.

(c) Increase the pull-up/down buffer resistance
Increasing the resistor value flattens the waveform, but reduces the current through the resistor.

(d) Utilization of power-down mode
Blocks that support power-down mode frequently enter power-down mode when they do not need to operate.

How to lower Ileak

The most effective ways to reduce leakage are increasing Vt (threshold voltage) and power gating.
Intel supports both of these low power techniques.

(a) Method of increasing Vt (threshold voltage)
Vt (threshold voltage) is the voltage that acts as a divider to distinguish logic low and logic high.
For example, increasing the height of the threshold will make it harder for the charge to cross the threshold, so the leakage current will decrease, but it will also make it harder for the charge in normal operation to cross the threshold, so it will slow down.
Thus, increasing Vt greatly reduces leakage current, but at the cost of speed. It's similar to hurdling.

With Intel's Programmable Power Technology, Quartus ^® Prime automatically lowers Vt for critical path parts for faster speed, and raises Vt for other parts for lower power.
This method is highly effective because there are few critical path parts in the entire circuit.

In the future, the timing accuracy of Quartus Prime will be further improved, the range of Vt increase will be greater, and if Vt can be dynamically controlled, the effect will be even greater, so it is a promising low-power technology.

Competing FPGA vendors say that this programmable power technology is only evaluated by dynamic power and is less effective, but it is a technology that mainly reduces leakage power.

(b) Power gating
Power gating is a function that cuts off power to unused circuits.
Intel has started supporting power gating in DSPs, memory cells, etc.

If the dynamic power gating of the logic part becomes possible in the future, it will be possible to greatly reduce leakage power, so it is a promising technology for low power consumption.

(c) Small chip area
To reduce the chip area, there are two methods: making the circuit smaller and using a finer process.
The leakage power of miniaturized FPGAs is high, but the chip area becomes smaller due to the larger circuit scale.
The increase in power consumption using the latest process FPGAs is due to the increase in circuit size and speed.
The power consumption values announced by FPGA vendors look low because they are compared with the same circuit size and speed.

(d) Partial reconfiguration
Partial reconfiguration is a function that changes the circuit configuration of some blocks during operation.
Since unused circuits are turned off, the leakage power of those circuits can be reduced.

(e) lower the temperature
Subthreshold leakage current, which is currently a problem, is highly dependent on temperature, and it is said that if the temperature rises by 50°C, the value will increase tenfold.
Leakage power can be reduced by lowering the dynamic power or by considering the cooling method and board layout to lower the chip temperature.
Siemens EDA's HyperLynx Thermal Although it is not possible to strictly analyze the heat of the board, it is recommended because it is inexpensive and anyone can easily disperse the heat generated by the FPGA.

(f) Decrease Vcc
7th As for the method I introduced, lowering Vcc also reduces leakage power.
-SmartVID
“SmartVID” lowers Vcc, thus reducing leakage power.
-VCC Power Manager
“VCC PowerManager” lowers Vcc, thus reducing leakage power.

(g) Low static power device grade
Intel offers "Low Static Power Device Grade" FPGAs that consume less static power than standard power devices while maintaining performance.
Leakage power can be reduced simply by using this device.