I was able to understand what was done in each process, but I couldn't get an image of logic synthesis and placement and routing. Therefore, this time I will study about logic synthesis and placement and routing.

Logic synthesis is to optimize the circuit written in HDL or the circuit written in Block Diagram / Schematic File. Take the figure below as an example.

　1 の図をよく見ると青丸で囲まれた部分が無駄であることがわかると思います。これではリソースも無駄に使われてしまうことになってしまいます。論理合成ではこのような論理の無駄をなくしてくれます。1 の図を実際に Quartus II で論理合成した結果が 2 の図です。ここでは青丸の部分がただの配線として処理されています。

Incidentally, in Quartus® Prime, you can perform logic synthesis by pressing the button shown in the image below or by selecting "Start Analysis & Synthesis" from the "Processing" menu.

Placement and routing is to decide how to place the logic-synthesized circuit on the actual device and how to wire it. Take the figure below as an example.

An FPGA consists of a large number of logic elements (LE) and the wiring that connects them, as shown in the figure below. Depending on the design size, many LEs are used to realize the circuit after logic synthesis. Placement and routing determine where to place the large number of LEs and how to connect them.

Furthermore, Quartus® Prime has a feature called Chip Planner that graphically displays the results of the placement and routing. This allows you to see which LEs are being used and how they are routed.

Incidentally, in Quartus® Prime, you can perform placement and routing from the Start menu to Start Fitter in the processing menu.

Until now, I was doing logic synthesis and placement and routing without understanding what I was doing, so I sometimes wondered, "Is it all right?"

But with this, I was able to understand what was done in logic synthesis and placement and routing.

From now on, I would like to introduce more and more things that I did not understand during the training.