Reason why all bits do not change at the same timing

The reason is that the input clock edge for each register is different.

Each has a different time to reach the clock input of the register.

1. Clock delay to register 1 = routing delay from input clock pin
2. Clock delay to register 2 = _tco of register 1 + routing delay
3. Clock delay to register 3 = _tco of register 2 + routing delay

*tco is the time from clock input to register data output

The tco of each register is a fixed value depending on the device.

wiring delay

Figure 2 below is an image diagram of the internal structure of an FPGA device.

Where the circuit of the asynchronous counter (Figure 1) is placed on the FPGA device and which wiring is used depends on the compilation.

In the asynchronous counter, the output of one register is the clock for the next register, so the clock delay varies depending on the wiring status.

This is the reason why the data change point of the aperiodic counter is different for each bit.

Next time is the conclusion.