During the clock making practice, I was told that I should at least configure the AS mode, not just the JTAG-only configuration mode.

It is true that there is a high probability that the logic will be incorrect in production practice, so JTAG configuration, which allows rewriting of FPGA data each time, is optimal, but it is difficult to think that JTAG configuration is optimal for your product.

Writing to products installed in various places one by one with JTAG means that engineers have to stick to each product.

Labor costs are too high. . .

So I checked the configuration.

They can be classified into three types according to what is used for configuration.

・Using an Altera download cable

・Uses serial configuration memory

・Using general-purpose parallel flash memory

I would like to give you the pros and cons of what kind of configuration you should propose to your customers.

Configuration modes include:

・Active Serial (uses serial configuration memory)

・Active Parallel (using external control circuit or program + general-purpose parallel flash memory)

- JTAG (using Altera download cable)

・Passive Parallel (uses general-purpose parallel flash memory)

・Fast Passive Parallel (using external control circuit or program + general-purpose parallel flash memory)

Serial and Parallel, as they say, mean whether the configuration data is serial data or parallel data.

・Serial: Configuration data is serial

・Parallel: Configuration data is parallel

It can be inferred that parallel data will result in faster configuration times than serial.

Active and Passive seem to represent which side the clock is driving from.

・Active: Cyclone® IV device outputs clock for configuration

Passive: Cyclone IV device receives configuration clock

It makes sense when you recommend Active Serial (AS) mode.

For those of us who find it difficult to create a control circuit or program for configuration, we found that the Active Serial mode, which enables configuration by simply connecting as described in the handbook, is the most suitable.

My question is, how does the device know about multiple configuration modes?

This information was found in the Cyclone IV handbook, Volume 1, Chapter 8: Configuration and Remote System Upgrades.

The FPGA's MSEL pins now select the configuration mode.

At the stage of research and development, configuration in JTAG mode is recommended, but in the case of mass-produced products, the mode that should be proposed depends on the product specifications.

If you want to achieve configuration easily, you can use AS mode, which uses serial configuration memory. If you can't increase the number of parts, you can use a combination of CPU + general-purpose flash memory, which is already planned to be used for other functions. .

If the configuration fails, it becomes just a board. . . I understand that configuration is important.

The configuration mode is now set. Next you need to select Altera's configuration memory.

In the next installment, we plan to introduce the selection of the configuration ROM.