Reduction of core voltage (VCC)

Core voltage has a significant impact on power consumption, but it's difficult for designers to change the core voltage.
However, Altera offers many options for lowering the core voltage, so please take advantage of them.

(a) SmartVID
SmartVID is a method that allows you to operate at the specified speed while reducing power consumption.

Due to manufacturing variations, even among FPGAs, some devices operate faster than others.
Altera writes the minimum voltage required to maintain operation to the device during shipping tests.
This value is called "SmartVID".

For example, if an FPGA has a base voltage of 0.9V and a SmartVID voltage of 0.8V, it will operate with 20% lower switching power ((0.8/0.9) ^²). In addition, lowering the voltage also reduces leakage power (up to 40% reduction on the ^Arria® 10).

(b) VCC PowerManager
VCC PowerManager is a way to reduce power consumption, although it will slow down the process.
High-speed grade devices have ample speed capacity, so power consumption can be reduced by deliberately lowering the speed (reducing the voltage).
For example, if performance is the priority, use 0.95V, and if power is the priority, you'll use 0.9V, although the speed grade will be one or two steps lower. Of course, you can verify the timing with ^Quartus® Prime at either voltage.

Parallelization and pipelining are methods to compensate for the slower speed.
Incidentally, there are examples of this in ASICs, such as the following: ^Stratix® 10's speed is doubled through pipelining, so VCC PowerManager is an effective method.

(c) Power Gating
Clock gating is a method of "stopping the clock" of a block only when it is not being used.
Power gating is a method of "turning off the power" only when the device is not in use.

For information on clock gating, please refer to Column #8.
Altera has begun supporting power gating in its DSPs and memory cells.

(d) Programmable Power Technology
When compiling a design in Quartus Prime, if there is sufficient timing, use the low-power mode with a raised threshold. This significantly impacts leakage power and, because the threshold is changed, also affects dynamic power.

(e) Low-voltage devices
Altera FPGAs include families that offer low voltages in addition to the standard voltage.
This FPGA allows for low-voltage operation.

(f) Devices with the latest processes
As the process becomes newer, the core voltage decreases, so simply switching to the latest FPGA will lower the core voltage.
However, in circuits with slow operation, the proportion of leakage power increases compared to dynamic power, so older processes may have lower total power consumption.

Reduced signal amplitude (Vs)

(a) I/O of small signal amplitude
Using small amplitude I/O reduces power consumption.
Small amplitude I/O is not only low power consumption but also high speed, making it an I/O type that should be used actively.

Altera offers many options for lowering the voltage.