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In this column, we will introduce "technical information on FPGA that is surprisingly unknown, but makes a difference if you know it."
From FPGA beginners to veterans, the contents can be used widely, so please keep in touch with us until the end.
[Part 1] Three Principles for Low Consumption
As the size of FPGAs has grown, power consumption has become an issue.
In this column, I would like to write mainly about low power consumption measures that designers can take.
First of all, low power consumption design methods include methods that can be done by designers and methods that can only be handled by semiconductor vendors.
Effective low-power techniques that designers can implement include:
(1) Take countermeasures as early in the design process as possible
(2) Replacing analog circuits with digital circuits
(3) Replace part of software processing with hardware processing
Correspond at the design upstream as much as possible
The effect of measures to reduce power consumption increases in the following order.
Netlist < RTL < Algorithm
In most of the netlisted circuits, the effect is only a few percent except for the clock system.
Algorithm-based countermeasures can reduce power consumption by several tens of percent or more.
Just being conscious of low power consumption when designing algorithms has a great effect, so in the next column and later,
I would like to mainly introduce know-how that is useful when designing algorithms.
Replace analog circuits with digital circuits
Power consumption can be reduced by replacing analog ICs with digital circuits and placing them inside FPGAs.
General digital circuits are mainly CMOS circuits, so power consumption is low. And once analog circuits are replaced with digital circuits,
Power consumption can be reduced simply by replacing with the latest FPGA, which is being miniaturized one after another.
Analog circuits tend to have better characteristics in older processes than digital circuits.
It is difficult to reduce power consumption through miniaturization.
Replace part of software processing with hardware processing
As it became difficult to increase operating frequencies, software processing devices such as processors, GPUs, and DSPs began parallelizing their cores.
Since FPGAs can be parallelized in smaller units, they consume less power than these devices because they do less wasted work.
Replacing frequently used functions and performance-requiring parts from software processing to hardware processing can significantly reduce power consumption.
If the algorithm changes frequently, it is convenient to use a high-level language such as OpecCL.
For example, by replacing the GPU used as a server coprocessor with an FPGA, power consumption can be reduced by an order of magnitude.
FPGAs are attracting attention in the HPC (high-performance computing) industry.