Microchip FPGA: About REFCLK placement constraint rules. When using the GUI in Libero SoC's I/O Editor => XCVR View tab, clocks can be supplied to all TXPLLs and Lane_Quads by using REFCLK at the top. There are lane quads that cannot be connected depending on REFCLK placement. Please give me accurate information about this constraint.

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Microchip FPGA: REFCLK placement constraint rules. When using Libero SoC's I/O Editor => XCVR View tab GUI, REFCLK at the top can be used to supply clocks to all TXPLL and Lane_Quad. There are lane quads that cannot be connected depending on the REFCLK placement. Could you please give me the exact information about this constraint?

Libero SoC PolarFire Clock/CCC Transceiver

Can only be connected below (Cascade to Lower) a specific REFCLK, not above.
For more information, see UG0677: PolarFire FPGA Transceiver User Guide
https://www.microsemi.com/document-portal/doc_download/136531-ug0677-polarfire-fpga-transceiver-user-guide
Please check the Cascade to Lower limit in the figure in 3.5.4.1 Transceiver Reference Clock Interface.

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