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For DDR operation LVDS, the maximum input/output is 1.0 Gbps for the WLCSP36 package, and 1.2 Gbps for other packages (half the clock frequency).

On the other hand, in the case of 7:1 LVDS format such as channel link, it is as follows ("fMAX_RX71_141", "fMAX_TX71" in the data sheet. Internal clock frequency is 1/2, external parallel clock frequency is 1/3.5)
Input: Up to 900Mbps per lane for all packages
Output: Up to 1.0Gbps per lane for WLCSP36 package, up to 1.05Gbps per lane for other packages