Use the Timequest Timing Analyzer. If there are two clocks (CLK_A, CLK_B) and they are asynchronous, how do I write SDC to ignore the asynchronous path between CLK_A and CLK_B during timing verification?

Timing constraints/analysis

There is also a method to describe the settings individually for all applicable paths, but it is very time-consuming, and mistakes such as descriptions and omissions are possible.

If you want to ignore all paths between specified clock domains, this is very easily defined using the "set_clock_groups" command.

A description example is shown below.
set_clock_groups -asynchronous -group {CLK_A} -group {CLK_B}

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.