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Intel: What are the register settings for automatic flow control for the Intel® FPGA 16550 Compatible UART Core?
Category: IP (Other)
Tools: Nios® II EDS
device:-
You can check the necessary register settings by referring to the Nios® II HAL API Software provided with the 16550 UART.
The MCR must be set to 0x22 to enable the following registers.
MCR (5): Hardware Auto Flow Control Enable (afce)
MCR (1): Request to Send (rts)
(Reference) Software source
***_BSP > divers > src > altera_16550_uart_init.c > alt_16550_uart_config() line 352 and below
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