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Intel: When writing a .jic file to EPCQA on a board with Cyclone® V SoC, the peripheral buffer and FPGA heat up only during the write. why?
Category: Programming/Configuration
Tools: Quartus® Prime
Device: Cyclone® V
This is due to incorrect unused pin settings in the Serial Flash Loader (SFL) image included in the .jic file generated by Quartus® Prime.
■ Countermeasures
Download the SFL library included in .jic from the following site and replace the existing library.
■Target device
Cyclone V SE - Member Code A5, Package F896 (31mm)
Cyclone V SX - Member Code C5, Package F896 (31mm)
Cyclone V ST - Member Code D5, Package F896 (31mm)
Why do some GPIO pins drive low during JIC programming in Cyclone® V SoC devices?
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2019/why-do-some-gpio-pins-drive-low- during-jic-programming-in-cyclon.html
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