Category: DSP
Tool: DSP Builder
device:-


A testbench is automatically generated for the HDL simulation with exactly the same inputs and outputs as the Simulink® simulation works.
The user should take care when building the model so that the filter characteristics can be seen in the Simulink simulation.

[Procedure overview]

1. Model the design you want to FPGAize with the DSP Builder block. At that time, I/O is created with Simulink original blocks, etc., with an awareness of characteristics confirmation for Simulink simulation.
2. Run a Simulink simulation to confirm that the model characteristics are what you intended and that there are no problems with the design. At that time, if the generation function is turned on, both the HW HDL and the test bench for ModelSim® simulation will be generated.
3. Launch ModelSim® from DSP Builder and direct the HDL simulation. The test bench applies the same input and output values as the Simulink simulation using the dump file, and the exact same behavior as the Simulink simulation is confirmed in the HDL simulation. (In the unlikely event that there is a mismatch for some reason, a message will be displayed.)

Please refer to the handbook for detailed instructions.
https://www.altera.com/en_US/pdfs/literature/hb/dspb/hb_dspb_adv.pdf