Overview

SLVS-EC Rx IP is an IP for realizing SLVS-EC reception in Intel® FPGA. SLVS-EC is a high-speed serial interface standard for high-resolution CMOS image sensors proposed by Sony.
This standard employs an Embedded Clock that embeds a clock in pixel data, enabling board design without being aware of the skew that occurs between lanes. Therefore, it is advantageous for high-speed and long-distance transmission.

Features

• Compatible with SLVS-EC Specification Version 1.2/2.0
• Implements various functions defined by SLVS-EC Link layer (Physical layer is implemented by Intel® PCS/PMA)
• Supports Byte to Pixel conversion in various lane configurations
• Includes header parsing and payload error detection

specification

* Baud Grade 3 is supported only for 10 series or later
* CRC may not satisfy the operating frequency depending on the speed grade and number of lanes of the FPGA used.
* Please contact our sales department for unsupported IP functions and restrictions.

corresponding device

• Cyclone® V-GX
• Cyclone® 10GX
• Arria® 10 GX
• Stratix® 10 (L-Tile/H-Tile)
  (*Please contact our sales department for the compatibility status of other devices.)

Offerings

• Cryptographic RTL (Verilog HDL)
• Reference design
• Simulation environment (for Modelsim)
• User's Manual, Reference Manual, Simulation Manual

logic resource

It becomes a circuit configuration including Transceiver with 8 lane configuration.

* The above value is an approximate value of the circuit scale with the total of 8Lane Full Configurable and IP + Transceiver. It may vary depending on the customer's system configuration.

Evaluation/demo environment

This IP can be evaluated and demonstrated using our EasyMVC Machine Vision Camera Development Kit.

Inquiry