Clock design for FPGAs is getting more complex

All of a sudden, it started like a threat, but...
"FPGA", which can be said to be the center of hardware systems, has undergone various evolutions in recent years, although there are some differences depending on the lineup, and the complexity of peripheral design has increased.
The I/O standards have been upgraded with various hard IP blocks and high-speed SerDes to support multiple interfaces such as Gigabit Ethernet, PCIe, and DDR memory.
Therefore, in the first half of this article, we have summarized the points you need to know for customers who are "choosing clocks for FPGAs" these days with complex clocking requirements.
In the second half, we will introduce SiTime's "clock solution" for "not failing in component selection".
By all means, please try combining it with FPGAs such as Intel Corporation, Lattice, etc. that we handle. (with reference design)

Clock selection for FPGA is very important

So, what kind of clocks are there for FPGAs?

Recently, each FPGA manufacturer has added several built-in PLLs, so I listed them with that point in mind.

■ Clock example for FPGA

・ Reference clock for built-in PLL inside FPGA
・ Reference clock for each I/O
・ Clock for user logic
Various clocks to support functions such as real-time clock (RTC)

Depending on the performance and design of the selected FPGA, external logic ICs may be added to the periphery. CPU, flash memory, etc.
The clocks required for these must also be covered at the same time.
In addition, custom ASICs are not satisfying the development cost and development period, and the number of cases where FPGAs are used in a wide range of applications is increasing.
It is very important to select a clock manufacturer that "provides stable performance in a variety of applications and environments."​

“SiTime Clock” Solution for FPGA

■ Three reasons why SiTime should be used for FPGA clock
・Part 1: Excellent reliability in harsh environments

Four times better peripheral vibration than conventional clocks. Typical: 0.1 ppb/g

・Part 2: Guarantees excellent frequency deviation specifications over a wide temperature range

・Maximum operating temperature range: -55 to +125°C

・Airflow and heat resistance 1 ppb/°C

・Part 3: Must be a programmable clock

・Frequency, deviation, output type, etc. for both oscillator and clock generator can be freely programmed according to your request.

・Flexible response to detailed specification settings and sudden design changes

Device type	Recommended model number/series * Detailed specifications can be confirmed from the link for each product	Features
oscillator (single-ended)	SiT8008 SiT8009	・The simplest SPXO (general-purpose package oscillator) ・Many replacements from crystal oscillators (compatible) ・Support from 1 to 137MHz
oscillator (differential)	SiT9375 SiT9501	・Low jitter ・Compatible with differential interfaces such as LVDSLVPECL and HCSL ・Adopted industry's smallest size 2.0mm×1.6mm (A wide range of other sizes are also available)
Oscillator (precision TCXO)	SiT5501 SiT5503	・Excellent frequency deviation (±0.005ppm) ・Ideal for communication equipment used in harsh environments such as outdoors
clock generator	SiT95141	・Supports up to 10 outputs Corresponding frequency is below 8 kHz to 2.1 GHz (differential) 8kHz to 250MHz (LVCMOS) ・Integreted Phase Jitter：120fs ・ No need for an external crystal oscillator

Reference material (source: SiTime Corporation)

This time, we introduced the points when selecting a clock for FPGA and SiTime's clock solution so that you don't have to worry about clock design for FPGA.
I hope this article has been of some help to you. Please feel free to contact us if you have any questions during the design process.

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