Reasons why SiC FETs can be easily replaced

Qorvo's SiC FET product line is built on the core technology of high voltage normally-on SiC JFETs combined with low voltage normally-off Si MOSFETs in a cascode configuration.

Qorvo's SiC FETs are cascoded, making them easy to drive. Figure 1 is a simplified diagram of the cross-sectional structure of a general SiC MOSFET and Qorvo's SiC FET. In general, SiC MOSFETs require a negative voltage such as -5V to turn them completely off, and a high voltage such as +15V to turn them completely on.

In addition, some products can only tolerate an absolute maximum VGS rating of -7V. This is because the general SiC MOSFET has a channel structure, and there is no margin for the absolute maximum rating of VGS.

Figure 1. Schematic cross-section of common SiCMOSFET and Qorvo SiC FET

Figure 2 is a graph of the VGS recommended operating voltage and absolute maximum rated voltage for each device.

As can be seen from this graph, general SiC MOSFETs are used in a state where there is no margin, and if the absolute maximum rated voltage is exceeded, the life of the device will be affected. Looking at Qorvo's SiC FET, the VGS recommended operating voltage is 0 to 12V, and the absolute maximum rated voltage is ±20V, so the value is at the same level as a general Si MOSFET. . Qorvo's SiC FETs are much more robust than SiC MOSFETs and offer a wide range of options for gate drive circuits.

Figure 2. VGS recommended operating voltage and VGS absolute maximum rated voltage for each power device

Qorvo's SiC FETs are easy to replace because they can use the gate drive circuits of conventional power devices as they are.

The most important factor when considering a drop-in replacement from the current situation is the gate drive voltage. The VGS absolute maximum rated voltage of Si MOSFETs and Si IGBTs is generally ±20V. Some conventional Si MOSFETs have a limitation of -5 to -10V on the negative side. Also, the gate threshold voltage is approximately 5V and is normally OFF, so no negative drive voltage is required. Normally +12V~+15V is used to turn ON.

On the other hand, a typical SiC MOSFET has a low gate threshold voltage of approximately 2.2V. It requires a negative gate voltage during OFF to avoid false turn ON. And a voltage of +15V to +20V is required for complete ON.

Qorvo's SiC FET has a gate threshold voltage of 5V, the same as Si devices, and is normally OFF. No negative voltage is required for gate drive. Considering the replacement with Si MOSFET and Si IGBT, it can also be driven at 12V. Of course, there is also sufficient withstand voltage in the negative voltage direction, so there is no problem using a drive circuit that swings from -5V to +20V for driving a general SiC MOSFET. Qorvo's SiC FETs can easily replace SiC MOSFETs, Si IGBTs, and Si MOSFETs.

Figure 3. Comparison of Qorvo SiC FET and SiC MOSFET

ESD immunity of SiC FETs

A SiC FET in a cascode configuration of SiC JFET and Si MOSFET, the Si MOSFET is connected to the gate and source terminals of the package, which limits the ESD performance. JFETs are PN junctions and can handle much more ESD than MOSFETs. Qorvo's MOSFETs use integrated diodes for ESD protection, and the Si MOSFET size and capacitance are the determining factors for ESD performance.

Figure 4. Basic cascode configuration with Si MOSFET drain connected to SiC JFET source (left).
Cascode configuration with back-to-back diodes from Si MOSFET gate to source pad (right)

Qorvo's entire SiC FET portfolio uses a family of MOSFETs scaled to JFET size and RDSon. The smallest JFET requires the smallest MOSFET, and these limit the ESD rating of the part. This also means that only the MOSFET is ESD tested to determine the ESD rating of all products using that MOSFET.

In the charged device model, all MOSFET samples were tested to ±2000V and passed. This makes the part CDM Class C3 (> 1000V). For human body model testing, all MOSFET samples were tested up to ±8000V on each of the three terminal combinations. All MOSFETs passed up to 8000V across the drain-source terminal pair. Gate-source and gate-drain tests depend on device size. The smallest MOSFET passed 3900V gate-source and 3700V gate-drain.

All Qorvo devices are now set to a minimum HBM class H2 (2000V to 4000V). Larger SiC FETs with larger MOSFETs perform better than the H2 class. The two largest devices are rated for Class 3B (> 8000V).

SiC JFET ESD rating

Like MOSFETs, the Qorvo family of SiC JFETs scales with size, with the smallest devices being the most sensitive to ESD. Unlike MOSFETs, JFETs are essentially insensitive to ESD because they consist of PN junctions. Utilizing the smallest JFET in the lineup, charged device model testing was performed to ±1000V and human body model testing was performed to ±8000V for all terminal pairs. All JFETs are C3 class and H3A class respectively.

Figure 5: Unit cell in JFET structure with (a) no gate oxide and (b) two PN junctions (gate-drain and gate-source) highlighted.

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