clock gating

This is a method to stop the clock and reduce the power consumption of the clock net, multiplexer, register, and combinational circuits after the register. There are two caveats when using clock gating:
-Stop as close to the clock as possible
-Clock gating in a vendor supported manner

In one gate circuit, stop the clock at the root of the clock line before it branches because the effect will be low unless you stop the clock line as long as possible and as many registers as possible.

Also, if the clock line is stopped by AND, etc., the timing cannot be guaranteed (because it is no longer a synchronous circuit), and there is a possibility that glitches may appear on the clock, so please use the method recommended by the FPGA vendor to perform clock gating. please.

Intel offers PLLs that support clock gating.
Please use it because it clears the above two points and is highly effective.

data enable

For devices with clock gating constraints, or where there are more data transitions than clock transitions, use data enables to enable data signals and stop wasted transitions.

Leveraging PLLs

Blocks that require a low operating frequency use the PLL to lower the operating frequency.

resource sharing

Sharing resources reduces the number of operations and transitions by using common terms.
For example, Z = AB + AC reduces the number of transitions to Z = A(B + C).

No sharing of resources

Resource sharing transitions every time the common term is switched even if the input data remains unchanged.
If the input data has few transitions, the power consumption is lower if the resource is not shared because no switching operations are required.

For example, Figure 2 consumes power each time the adder inputs are switched (even if A and B do not transition) in addition to the power consumption of the added multiplexer.

Glitch reduction in arithmetic circuits

Arithmetic circuits generate many internal glitches before the output is determined.
Reducing this glitch can reduce power consumption.


(a) Align input timing
Aligning the input timings of arithmetic circuits can reduce internal glitches.
- Add a register to each input pin of the arithmetic circuit.
→The input timing becomes the same, reducing glitches in the arithmetic circuit.
- Change the operation order of all blocks to reduce the deviation of the signal input timing of the target block.
- Changed chain type to tree type
→ Since the number of stages is reduced, the input timing becomes closer.

For example, a 4-bit chain adder has about 45% more toggling due to glitches than a 4-bit tree adder.

Pipelining arithmetic circuits reduces logic depth and reduces glitches.

In some cases, flattening a structured circuit reduces power consumption, so please check with the actual device.
(There is a possibility that it cannot be verified with a power simulator.)

(b) pipeline
Large arithmetic circuits are divided into smaller circuits and pipelined.
Glitches due to delay differences in signals passing through the arithmetic circuit are greatly reduced.

Optimizing Number Representation

(a) Bus invert encoding
A technique that reduces the number of bus and adder transitions.
Bus invert encoding is a useful technique for randomly varying data buses.
Specifically, when more than half of the data in the previous clock has changed, the control signal is raised to invert the data. The data bus has an extra bit for control signals.

(b) Gray code or Johnson counter
A technique for reducing the number of consecutive data transitions on buses and counters.
Gray code counters and Johnson counters have fewer transitions than binary counters because they only transition one bit each time they count.

Each example for 3bit is shown below.
The Johnson counter circuit is simple, but it can represent fewer numbers.
In the example below, the state values 010 and 101 do not exist in the Johnson counter.

The number of transitions in Gray code is 1/2 to 1/1 that of binary code, and the greater the number of bits, the greater the effect.

(c) 2's complement sign-magnitude representation
2's complement is often used because it is easy to add or subtract negative values, but in 2's complement, all bits change when "-1" changes to "0". Therefore, using the sign-magnitude representation reduces the number of transitions and reduces power consumption, rather than using two's complement.
The sign-magnitude representation is a representation in which one bit is assigned to the sign and the remaining bits are used to represent the absolute value of the data.

Change multiplier to shift-adder

Changing the multiplier to a combinational circuit of shift circuits and adders reduces the number of transitions.
For example, the multiplication operation Z =X *8 has the same result with only three shifts using a shift register, but with significantly fewer transitions.

output buffer

Since the output buffer drives external wiring with a very large capacity, it should be designed so that it outputs signals only when necessary, or outputs signals after glitches subside and the output stabilizes.

Pre-computation

If you decide that you don't need to do some calculations first and have the whole thing work, stop the work and reduce the number of transitions.

For example, an n Bit comparator will compare all bits even if the result is known to be the same.
Therefore, first compare only 1 bit of MSB, and compare other bits only when the value is the same. Then, if the magnitude is known from only one MSB bit, the transitions can be greatly reduced because other bits are not compared.

Operand isolation

Since the arithmetic circuit is composed of combinatorial circuits, the internal logic frequently toggles until the result is determined.
When the calculation result is unnecessary, stop the input signal and stop the internal operation of the arithmetic circuit.

For example, if there is a multiplexer at the output of the arithmetic circuit, use the select signal to stop the input data. This is used in multi-bit arithmetic circuits.

Separation of buses

The number of transitions can be reduced by dividing the bus rather than by sharing the bus for time-division operation.
Also, if the number of transitions between the lower bits (LSB) and the upper bits (MSB) is significantly different, separating the buses can reduce power consumption.

For example, RAMs with large word widths may reduce power consumption by comparing the transitions of the most significant bits (MSBs) and the least significant bits (LSBs) and splitting the words using a multiplexer.
This is because lower bits generally transition more often than higher bits.

Take advantage of code coverage

Run code coverage to reduce dead circuits that aren't working.

fine-grained parallelism

FPGAs consume less power than multiprocessors or GPUs because the granularity of parallel processing is small.
Power consumption is reduced when the processing performed by the processor or GPU is processed by the FPGA.
It is also possible to convert the program that was doing software processing to FPGA with OpenCL SDK.