Altera® Cyclone® 10 GX FPGA: Circuit Diagram Check Points

Narrow down by specifying conditions

現在2159件がヒットしています。check

Design FPGA/CPLD/ASIC boards Altera Corporation

When creating a board to mount an Altera® FPGA, designers create a circuit diagram by referring to the documents published by the manufacturer.

Here, we will guide you to the points that you should pay special attention to.

The Altera® Quartus® Prime design software (hereafter referred to as Quartus Prime) also allows you to check placement based on various device constraints.

In addition to checking the circuit diagram with reference materials, please also check with Quartus® Prime.

Target FPGA

・ Altera® Cyclone® 10 GX

Advance preparation

Here are some documents that can be used as reference when creating circuit diagrams.

Pin connection guidelines

Schematic review worksheet

Pin Connection Guidelines (All Devices Except Agilex™)

*Altera® Agilex™ familyHere

Schematic Review Worksheet Top Page

Cyclone ^® 10 GX Device Family Pin Connection Guidelines

Cyclone ^® 10 GX Devices Schematic Review Worksheet

Cyclone® 10 GX Overview (FPGA TOP)

The figure below shows the pins that need special attention when designing the Cyclone ® 10 GX board.

* The layout in the diagram has nothing to do with the actual device.

Click each item to see the check points.

① VCC, VCC for HPS, VCC for transceiver	② MSEL pin	③ Configuration pin
④ JTAG pins	⑤ Clock input pin	⑥ Other dedicated pins
⑦ Transceiver Pins	⑧ DDR3 pin	⑨ Multipurpose pin
⑩ I/O pins	―	―

① VCC, VCC for HPS, VCC for transceiver

● Establish a measurement point near the FPGA

・Be ready to measure the power supply in case of trouble

・Refer to Power & Thermal Design & Debugging Guidelines

● If all transceivers, fPLLs, and IOPLLs on the same side are unused,

VCCT_GXB can be connected to GND (Check pin connection guidelines for details)

● Decoupling capacitor

・Estimate with reference to the PDN tool

・For a more detailed estimate, use a dedicated tool

　　Power Delivery Network (PDN) Analysis Tool

　　Part 9 Confirmation and Review of Capacity in FPGA Power Supply Design

● Power sequence

For more information, please see this document (Power Sequencing Considerations for Altera® Cyclone 10 GX Devices).

▲ Back to Cyclone 10 GX Overview

② MSEL pin

Please see below for Cyclone 10 GX MSEL pin information.

MSEL Pin Settings

Inserting pull-up/pull-down resistors⁽¹⁾⁽²⁾

Cyclone 10GX

* Refer to "MSEL Pin Settings" on the link

unnecessary

(see linked documentation)

(1) A Weak Pull-Down Resistor (25kΩ) is inserted inside.

(2) If you want to switch the configuration mode, insert a 0Ω resistor to switch to VCCPGM/GND.

(3) Do not drive the MSEL pins with a microprocessor or other device.

See here for a list of MSEL pins.

▲ Back to Cyclone 10 GX Overview

③ Configuration pin

● DCLK

・Recommend inserting damping resistor (minimum 0Ω) 10-50Ω

・In AS mode, take care of the trace length (see the document below)

　　Trace Length Guideline (from “Configuration, Design Security, and Remote SystemUpgrades in Altera® Cyclone 10 GX Devices”)

● nCONFIG, nSTATUS

・Pull up to VCCPGM via 10kΩ resistor

● CONF_DONE

・Pull up to VCCPGM via 10kΩ resistor

・Do not connect to the LED as it is.

- Due to lack of drive current, it may not light up without applying FET

● CLKUSR

・ Must be entered before configuration

- For AS mode, input 100MHz clock

- For PS, FPP mode, input 100 ~ 125MHz clock

・When using a transceiver, use CLKUSR as the calibration clock (required)

● For migrating from EPCS/EPCQ to EPCQ-A, refer to AN822: Altera® FPGA Configuration Device Migration Guideline.

● When FPGAs are cascaded, nSTATUS and CONF_DONE are pulled up in common.

● nCE

・Connect to GND for single device configuration.

・This signal determines whether the FPGA is cascaded.

● When using nCEO, pull up to VCCPGM through a 10kΩ resistor.

▲ Back to Cyclone 10 GX Overview

④ JTAG pins

● Check Point

・It is recommended to insert a 0Ω damping resistor for TCK.

- To support cases where writing is not possible due to problems with the clock system

● Pin processing

・TCK: pull down via 1kΩ resistor

・TDI: Pulled up to VCCPGM via 1kΩ to 10kΩ resistor

・TMS: Pulled up to VCCPGM via 1kΩ to 10kΩ resistor

・TDO : No pull-up/pull-down

・TRST : Option used. Pull up to VCCPGM through a 1 kΩ resistor if unused.

● When cascading three or more FPGAs, insert buffers on the TCK and TMS lines.

▲ Back to Cyclone 10 GX Overview

⑤ Clock input pin

● When using a single-ended clock, assign it to the p-channel

(Does not ride on global clock directly on n-channel. Limitation when using ALTCLKCTRL buffer)

● Pay attention to AC/DC coupling when inputting differentially.

● If you are using a PLL, pull down the RREF pin through a 2kΩ resistor (resistor accuracy is ±1%).

● CLK and PLL pins can be left unconnected if not used.

* Refer to "Clock and PLL Pins" in Cyclone 10 GX Device Family Pin Connection Guidelines for clock input pin names.

▲ Back to Cyclone 10 GX Overview

⑥ Other dedicated pins

pin name	comment
RREF_[T,B][L]	Pulled down through a 2kΩ±1% resistor
VREFB*	Tie to VCCIO or GND in the same bank if not used as a dedicated pin
VREFP_ADC / VREFN_ADC	Connect to GND if not used as a dedicated pin.
TEMPDIODEp/n	Connect to GND if not used as a dedicated pin.

▲ Back to Cyclone 10 GX Overview

⑦ Transceiver Pins

● When not using the transceiver

・Clocks (REFCLK_GXB*_CHp/n) are individually connected to GND or collectively pulled down via a 10kΩ resistor.

・RX (GXB*_RX_*p/n) is connected to GND

・TX (GXB*_TX_CHp/n) is floating

● AC/DC coupling

・Adjust to I/O Standard

▲ Back to Cyclone 10 GX Overview

⑧ DDR3 pin

Please refer to the document below.

・ External Memory Interface (EMIF) Schematic Check Items [Altera® Cyclone® 10 GX FPGA]

▲ Back to Cyclone 10 GX Overview

⑨ Multipurpose pin

● Connect to GND if not used as a function pin and not used as a user I/O pin.

・ CLKUSR

・ DEV_OE

・ DEV_CLR

● If nPERSTL0 is used as a reset pin for PCIe hard IP, shift down the voltage from 3.3V LVTTL to 1.8V and connect it through a level translator.

▲ Back to Cyclone 10 GX Overview

⑩ I/O pins

The RZQ pin must be processed when performing internal calibration.

Recommended to use the RZQ pin to enable the internal calibration feature.

If using 2.5/3.0-V, check if the device supports it.

▲ Back to Cyclone 10 GX Overview

Appendix: Cyclone 10 GX MSEL Pin List

MSEL Pin Settings (FPGA Configuration)

Device Family	Configuration Mode	VCCPGM(V)	POR Delay	MSEL[2:0]
Cyclone 10GX	AS (x1, x4)	1.8	Fast	010
	AS (x1, x4)	1.8	Standard	011
	PS, FPP (x8, x16, x32)	1.2/1.5/1.8	Fast	000
	PS, FPP (x8, x16, x32)	1.2/1.5/1.8	Standard	001