explanation

To establish a high-density, high-performance Intel® Stratix® 10 design, it is important to plan the FPGA and system early in the design process.

“Design Guidelines for Intel® Stratix® 10 Devices” provides design guidelines for each stage of the design flow to increase productivity and avoid common design pitfalls.

Design Guidelines for Intel® Stratix® 10 Devices
https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/stratix-10/s10-guidelines-e.pdf

This document is a supplementary document summarizing points to be especially careful of in the "Design Guidelines for Intel® Stratix® 10 Devices". This document does not cover all points to note at the design stage, so please use it in conjunction with the document "Design Guidelines for Intel® Stratix® 10 Devices".

<Contents>

1. Device variations

2. Power supply design

3. Thermal design

4. Configuration

5. Debugging with SDM Debugger

<Appendix>

1. Automatic setting of JTAG clock frequency

2. Configuration settings

3. Device variations

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