Intel: I have installed all supported device families in the Intel® Quartus® Prime Pro Edition software, but I only see Intel® Cyclone® 10 GX FPGA in the device family selection screen.

Intel: Are there any restrictions on the placement of clock pins input to the PLL?

Intel: How can I calculate the latency of the PHY Lite for Parallel Interfaces Intel® FPGA IP?

Intel: Error(18101): An external memory interface or PHYLite IP core reference clock fed by a cascaded PLL. Connect the external memory interface or PHYLite IP core reference clock to an input buffer

Intel: How do I manually specify the location of the PLL Intel FPGA IP?

Intel: Error(332000): ERROR: You must run the read_atom_netlist command first to initialize the netlist

Intel: What is the purpose and range of values for the boot_scratch_cold0 to boot_scratch_cold8 registers in the System Manager group in the Intel® Stratix® 10 Hard Processor System Address Map and Register Definitions?

Intel: What settings improve Fmax in the interconnect section of Platform Designer?

Intel: Why does the output clock fluctuate when I choose Fractional-N PLL compared to Integer-N PLL?

Intel: When the Arria® 10 is powered off, is it okay to have external voltage applied to the I/O pins causing a floating voltage on VCCIO?

Intel: If I change the reference clock input of the Stratix® 10 GX PHYLite IP after the FPGA configuration is complete, does it matter if I reset the PHYLite IP?

Intel: I get an error when generating an IP with the IP Catalog in Quartus® Prime Pro Edition ver.21.1.

Intel: What is the burst behavior of the HBM2 (High Bandwidth Memory) IP core?

Intel: When issuing the RSU_IMAGE_UDATE command in Stratix® 10 RSU (Remote System Update), is there a rule for setting the addresses?

Intel: Example Design generation fails when using JESD204B IP with Wrapper Options = PHY Only setting on Stratix® 10 devices.

Intel: Error when creating and compiling CvP (Configuration via Protocol) update revision.

Intel: When using EMIF (External Memory Interface) IP in Arria® 10 or later devices, it is necessary to set I/O Standard in Assignment Editor for external pins for EMIF (DQ, DQS, Add/Cmd, etc.) mosquito?

Intel: What are the power-up time requirements for using Active Serial Fast Mode on Stratix® 10?

Intel: Are there any PCB design rules for Pad on Via in Intel FPGAs?

Intel: Synthesis fails when compiling the Example Design qts_pam4_com included in the Intel® Stratix® 10 TX FPGA Signal Integrity Development Kit installer.

Intel: From SoC EDS Command Shell of Quartus® Prime Pro Edition ver.19.3, Eclipse can be started normally, but bsp-editor cannot be started.

Intel: Can I use Triple Rate (up to 3G-SDI) and have different formats received for each transceiver channel?

Intel: Configure QDR II SRAM with Arria® 10. Can the Address/Command pins be placed freely at this time?

Intel: The Intel® Stratix® 10 Development Kit comes with 3 types of DDR4/DDR3/RLDRAM, which memory can I use with OpenCL™?

Intel: We are evaluating OpenCL™ on the Intel® Stratix® 10 Evaluation Kit. If you set it to PCI-Express 16 lanes and check with "aocl diagnose", the message "PCIe dev_id = 5170, bus:slot.func = 01:00.00, Gen3 x8" will be output for 8 lanes .

Intel: I would like to know the latency of the Transceiver Block for Arria® 10 devices.

Intel: I'm using the Transceiver PHY IP on Stratix® 10 and I get an error in the Fitter when I set VOD in QSF. Is it not possible to set Analog Parameters in QSF?

Intel: I'm trying to validate 100G Ether on my Stratix® 10 SoC (H-Tile). Is Ethernet Hard IP connected to the QSFP28 connector?

Intel: If the other device is reset during data communication and data is interrupted, is it necessary to take any measures such as inserting rx_analogreset, performing recalibration, resetting the entire transceiver, etc.?

Intel: I am using Stratix® 10 to configure PCI-Express (PCIe) IP and set MSI-X. When I check the Configuration Register it looks like All is zero. How can I get the expected value?