explanation

One of the advantages of FPGAs that has been considered in the past is that it is possible to change the pin layout, pin attributes, and circuit functions after the board is created and the device is mounted, and it is possible to deal with the risk of specification changes and design defects. You can

On the other hand, with the recent advances in performance of memories and interfaces, including FPGAs, many hard macros have been implemented in FPGAs, and complicated restrictions that need to be considered are increasing.
Also, since FPGAs are not necessarily upwardly compatible, there are cases where existing design resources cannot be used as they are.

For this reason, it has become essential to conduct sufficient feasibility studies in the preliminary stages of board design to reduce serious risks such as board revisions.

In this document, we created a skeleton design for verification in the feasibility study, and summarized the verification items and their confirmation methods.

The target device in this document is the Intel® Arria® 10 FPGA as an example, but can be used for all device families with the exception of device-dependent parts.

* Please use the latest version of Intel® Quartus® Prime to conduct the feasibility study.

<Contents>

・A case where the board was revised due to insufficient feasibility

·Checklist

・Feasibility study (feasibility study)

- Device selection

- create skeleton design

・Clock resource, IP, transceiver, I/O interface, Hard Processor System (HPS)

- Compilation of the entire skeleton design

- Check power consumption

- hardware verification (optional)

- Other notes

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