explanation

As the speed of memory interfaces increases, shrinking data valid windows and deteriorating signal quality are issues.

As the amount of time spent on verification and debugging to meet specification requirements tends to increase, it is important to design devices and boards according to appropriate procedures and to implement methods for debugging in advance at the design stage.

This document presents a “design flow” and a “debug flow”, and aims to prevent bugs from entering by designing in an appropriate procedure, and to quickly solve problems by implementing the mechanisms necessary for debugging. will do.

Target devices: Stratix® V FPGAs, Arria® V FPGAs, Cyclone® V FPGAs
Target memory standard: DDR2, DDR3(L)

<Contents>

Introduction
design flow
debug flow
Appendix
Checklist
How to check parameters
How to create Example Designs
EMIF Toolkit Usage Checklist

Document