Microchip FPGA: What is the equivalent of ModelSim ME Pro bundled with Libero SoC?

Intel: I'm using a FIXED license with a T guard key. I get an error when launching Questa* - Intel® FPGA Edition or ModelSim* - Intel® FPGA Edition.

Altera： 「MSVCR120.dll が見つからないため、コードの実行を続行できません。プログラムを再インストールすると、この問題が解決する可能性があります。」と表示されツールが起動できません。

Intel: I created a memory IP (ROM/RAM) in IP Catalog or Platform Designer and registered the initial values, but the initial values are not reflected in the RTL simulation results.

Microchip FPGA: If I implement the "ARM Cortex-M1 Processor Soft IP Core", is it possible to simulate the boot sequence with ModelSim ME?

Intel: How do I change the editor used by ModelSim* - Intel® FPGA Edition to an external editor?

Intel: How do I describe signals that use the FPGA's built-in pull-up when simulating with a simulator such as ModelSim®?

Intel: ModelSim* - Please tell me how to display Japanese in the built-in editor of Intel® FPGA Edition.

Intel: When I tried to simulate a PLL, there was a slight difference in the output clock frequency between the *.v file for RTL simulation and the *.vo file for gate level simulation. why is this?

Intel: How can I make the signal names displayed in the Wave window of ModelSim®- Intel® FPGA Edition to be short signal names instead of full paths?

Intel: A circuit using On-Chip Flash IP in MAX® 10 fails at Load when using ModelSim®-Intel® FPGA Edition for Nativelink simulation.

Intel: I have a proven design with RTL simulation of an ADC for a MAX® 10 FPGA in ModelSim®, and I ported it to a different directory and did the same thing, but I get an error message.

Intel: RTL level simulation of the ALTLVDS_RX IP fails at the "lvds_rx_reg_setting" parameter.

Mentor: ModelSim® limits the number of files to 30 when outputting files with $fopen in simulation. Please suggest me a workaround.

Mentor: Is it possible to customize the window layout and size when ModelSim® launches?

Mentor: I want to default ModelSim® compilation to System Verilog

Intel: Even if the simulation model of ALTERA_FP_FUNCTIONS is generated with Verilog specification for FPGA with 20nm process or less, the lower module at the end is generated as a VHDL file. Can't you simulate with VCS?

Intel: I am doing single port RAM generation and doing RTL simulation, but "altera_syncram" cannot find the module in "altera_mf.v", resulting in a simulation error. Please let me know the location of the library file where "altera_syncram" is defined.

Intel: ModelSim® and Questa® Sim versions were previously listed as 10.6, 10.7, etc., but from 2019, they are 2019.1, 2020.1, etc. It seems that 10.7 versions such as 10.7f are still being released after the 2019.1 release. What is the difference between these?

Intel: Design with DDR3 SDRAM Controller MegaCore supporting UniPHY fails in RTL simulation with Nativelink.

Intel: The Pro Edition does not have a "Generate Value Change Dump file script" option that causes Quartus® Prime to generate a script for VCD generation in EDA simulators such as ModelSim®. Please tell me how to set it.

Intel: How do I run PCI-Express (PCIe) Gen3 Root Port simulations on Arria® 10 devices?

Intel: When using the Cyclone® V DDR3 EMIF (External Memory Interface) IP, is it possible to check the values set in the mode registers (MR0-3) at the start of user mode through a simulation or actual device?

Intel: Does the simulation script generated by Tools menu > Generate Simulator Setup Script for IP in Quartus® Prime Pro Edition also include the user design files in the project?

Altera®：Questa® Sim のバージョン 2019.1 以降を使用して Quartus® Prime や Platform Designer 等で生成したシミュレーション用スクリプト（msim_setup.tcl 等）を実行すると下記のエラーが発生する場合があります

Intel: After running a simulation in Modelsin®, is there a way to later display signals that were not visible?

Intel: Added the Intel HLS Compiler generated IP to the Platform Designer system and generated a simulation model (VHDL). When simulating with ModelSim, my IP outputs indeterminate values.

Intel: When simulating with Nios®II, is there a way to reduce the time it takes for the main() function to fire?

Intel: Simulation model for ALTCLKCTRL IP generated in VHDL and compiled in ModelSim fails.

Intel: I am using a Mentor® Graphics simulator, which version should I use when simulating an Intel® FPGA design?