Intel: In Quartus® Prime Standard and Lite Edition 23.1, the Wizard screen crashes while creating ALTPLL.

Intel: Design Assistant feature cannot be selected.

Analog Devices Switching Regulators: Does the B/D option of the MAX77839 operate in skip mode at light loads?

Analog Devices RS485 Interface : What is the operating voltage range of the MAX3079E?

Analog Devices RS-485 Transceiver : What is the maximum communication baud rate for the MAX3483AE?

Analog Devices Switching Regulator : When using the MAXIM15465 in PFM mode setting, will it operate in PFM mode at light load and automatically switch to PWM mode when the load increases?

Analog Devices Switching Regulator : Can I get 300mA output when using the MAXM15465 in FPM mode?

Intel: In Platform Designer, if the reset polarity of a user-created IP is different from the reset polarity of an existing IP in the IP Catalog, does the user need to make any adjustments?

Intel: When I compiled HDL code written in arrays to infer memory for MAX® 10 FPGAs, it was placed in logic elements instead of memory blocks.

Intel: Modular ADC core Intel FPGA IP in MAX® 10 FPGA Single Power Supply Device, when using ADC Voltage Reference with Internal Reference, I can choose between 3.0V and 3.3V.

Intel: How do I manually specify the location of the ALTPLL?

Intel: What settings improve Fmax in the interconnect section of Platform Designer?

Intel: Which document specifies offset error (Eoffset) and gain error (Egain) for MAX® 10 ADC?

Intel: Is it possible to use the Jam STAPL Player to program configuration data into regions other than CFM0 of the MAX® 10 FPGA?

Intel: What algorithm does MAX® 10 FPGA use to detect CRC errors in user mode?

Diamond Tool displays the following warning message and compilation does not finish. Please tell me the measures. WARNING: The design is too congested to route. Maximum run time (3 hours) is automatically set.

What problems can be expected if there is voltage on the external pins while the XO2/3 are unpowered?

Please tell me how to read the specifications of CrossLink LVDS (7:1). There are two notations, UI and ns+(i+1/2)*UI, in the datasheet. What is the difference?

Analog Devices filter: LTC1068's "DC Offset Voltage" VOS2 has MAX.±25mV, but is the distribution of this error the same probability of 5mV and -5mV centering on 0V?

Intel: Are the analog-only input pins ( ANAIN1/ ANAIN2 ) for the ADC in the MAX® 10 FPGA Hot-Socket capable?

Analog Devices Automotive Audio Bus (A2B) : Is max 300mA guaranteed value for current IVSSN of "Negative Bias Switch" of AD2428W? Is it possible for device variation to drop below 300mA?

Intel: When using the Modular ADC core Intel FPGA IP alone and not in Platform Designer, is the reset input signal an asynchronous reset? How long should the reset period be?

Intel: Can I use Cyclone® V with the Intel® HLS (High Level Synthesis) Compiler?

Intel: JTAG not recognized in MAX® 10. The Exposed Pad on the back side of the EQFP package is not connected to GND, is this related?

Intel: Non-clock signal pll_lock_sync was reported in Unconstrained Paths => Clock Status Summary in Timing Analysis for designs with MAX® 10 PLLs. This signal is the Locked signal of the PLL, but why was it recognized as a clock?

Intel: Is it possible to change the delay value from the clock input pin in MAX® 10?

Intel: For a MAX® 10 single-supply device with all I/O Banks at 3.3V and no ADCs, is it okay to power them from one regulator?

How can I find unconstrained paths in Lattice FPGA timing analysis?

What is the LVDS data rate limit for CrossLink?

Intel: Does the Quartus® Prime Programmer have a Factory default PFL image for MAX® 10?