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Introducing Questa Lint

Out-of-the-box methodologies and goals

Questa Lint provides target checksets for FPGA design (CR), SoC design (CR), and IP design (CR), making it easy to set target-focused goals.
If your design project is FPGA, you can select the FPGA methodology checkset, the IP the IP methodology checkset, or the ASIC SoC methodology and apply it to your project immediately.

Overall design quality index

The graphical display of quality metrics is unique to Questa Lint. Categorize and score the analyzed results, provide the factors that influence their quality scores, and assess design verification quality based on lint results.
It is possible to grasp the quality of the design based on the score of the entire design, judge the risk and determine the priority of the work. Keeping the metric high helps reduce the total TAT for design verification.
The dashboard further breaks down the design quality metrics to graphically display statistics on problem analysis and response status, overall trends, and violations detected per module, per HDL file, and per check. I can.

debug function

GUI is supported as standard.
Supports navigation from displaying design information via GUI and pointing out violations in RTL code to detailed help for violations.
For structural violations, providing an analysis function on the schematic makes it easy to identify the cause of the problem.

status management

Manage team-level reviews with post-verification status updates, debugging, and assigning reviewers.
By integrating the status management mechanism, you can systematically manage problem indications, corrections, confirmations, and release criteria, and capture the progress of the project.