Formal verification techniques are used for checking, so no testbenches are required and the RTL is ready to run. Assertions are also automatically generated according to the check items, so even if you do not have knowledge of formal verification or assertions, you can easily check.
AutoCheck checks early in the design for functional issues that take a lot of time and effort to eliminate, such as dead code analysis, state machine deadlocks and livelocks, arithmetic overflows, out-of-bounds memory indexes, and more. automatically generate properties to find common design errors and corner-case bugs.
▶ Introduction of functions (Formal verification without testbench / Formal verification without assertion description / Exploring functions with cycle concept)
▶ Related information
▶ Seminar/Workshop
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Feature introduction
Introduces the main features of Questa AutoCheck.
Formal verification without testbench
Formal verification techniques are used to check for structural problems. This allows immediate execution and early verification without the need for a testbench, all you need is the RTL.
Formal verification without writing assertions
Assertions required for formal verification are automatically generated according to the check items, so even if you do not have knowledge of formal verification or assertions, you can easily check the structure of your design.
Exploring function with cycle concept
The main purpose of the lint check is to confirm reusability and pre-check before logic synthesis, and it checks based on code style and character (HDL). On the other hand, AutoCheck checks the circuit for rule violations. The difference between AutoCheck and lint check is that AutoCheck searches for circuits based on the cycle concept, and can detect bugs that lint cannot detect.
Related information
▶ How to download the Siemens EDA tool
▶ How to install Questa CDC/Formal
▶ How to license Siemens EDA tools
Seminar/Workshop
▶ [Online Seminar] Find Bugs Early with Automatic RTL Verification Without Testbench! <Free>
In this seminar, we will introduce a technique to automatically check for bugs hidden in RTL without the need for a testbench.
▶ Events and seminars related to Siemens EDA
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