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Design FPGA/CPLD/ASIC Intel® Programmable Solutions Group (now Altera Corporation)

In this column, we will introduce "technical information on FPGA that is surprisingly unknown, but makes a difference if you know it."
From FPGA beginners to veterans, the contents can be used widely, so please keep in touch with us until the end.

Power consumption

[Lesson 1] Three Principles for Low Consumption
[Lesson 2] Is clock gating (gated clock) effective?
[Part 3] Is this leak power? No, it's DC power.
[Part 4] Reasons why high-precision power simulators were not used
[Part 5] Is this the ultimate low power consumption method?
[Lesson 6] How to reduce the load capacitance (C)
[Lesson 7] How to reduce signal amplitude (Vs) and power supply voltage (VCC)
[Lesson 8] How to reduce operating frequency (F) and toggle rate (N)
[Lesson 9] How to reduce short-circuit power
[Lesson 10] How to reduce DC power and leakage power

Verification

[Part 1] What is the first thing you ask a designer who cares about design quality?
[Part 2] Verification methods not recommended for designs that have already been commercialized
[Part 3] Verification is a combination of various methods
[Part 4] More common defects in FPGAs than ASICs - asynchronous clocks
[Part 5] What is formal verification?

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Power consumption

Verification