What is an asynchronous clock error?

Asynchronous clock errors are glitches caused by racing or metastability when passing data between different clocks.

It malfunctions once every several hours, days, weeks, or decades on an actual machine, and there is no reproducibility even with timing simulations and actual machine verification.

As shown in Figure 1, when data is exchanged between clocks with different frequencies, depending on the timing difference between the clock and data, the data of the previous cycle may be captured at one time, and the data of the next cycle may be captured at another time. .
If this is a bus, only certain bits will be the data of the previous cycle and other bits will be the data of the next cycle. By the way, if it is the same clock, there is no problem because the setup and hold timing will be verified.

And if a clock enters during the setup or hold time of the post-stage register, it may become metastable. Metastable state is an indeterminate state (an intermediate potential that is neither "L" nor "H") for several cycles, which is a serious problem. There is no reproducibility even on the actual machine.

There is a method of verifying by shifting the clock and data back and forth (Clock: Min condition, Data: Max condition/Clock: Max condition, Data: Min condition), but even this method cannot verify metastability, which is troublesome.

See below for details on Metastable
https://www.macnica.co.jp/business/semiconductor/articles/intel/2129/

Why Asynchronous Clock Errors Are Troublesome

・Cannot be verified by "logical simulation"!
・Cannot be verified with "Timing Verification"!
・It may be found in "actual machine verification". But I can't reproduce it!

To analyze asynchronous clock errors, you need to follow the schematic or use a dedicated tool (CDC: Clock Domain Crossing).

"Soft errors" that are easily mistaken for asynchronous clock errors

Some people misunderstand that an asynchronous clock error is a soft error because the cause cannot be determined.

If it is a soft error, it is possible to reproduce the error unless the FPGA is reconfigured (reconfigured).
Soft errors change the logic of the circuit, but metastables do not. If you suspect a soft error, run the same testbench to see if it can be reproduced.

Selection of CDC (Clock Domain Crossing) tool

It is recommended to use the CDC tool to verify asynchronous clocks.
The CDC tool itself is easy to use, but "confirming pseudo errors" and "considering countermeasures" are very difficult, so
Here are some things to keep in mind when choosing a CDC tool:

・It can be verified by RTL in the design upstream!
Verification after logic synthesis requires man-hours, so it must be possible to verify with RTL.

- Easy-to-understand reports! (Because I get a lot of pseudo-errors)
If there are tens of thousands of pseudo errors, you will overlook important errors.
Easy-to-understand reports are a must, as spurious errors require manual checking of the circuit.

- It must have a function to determine whether or not a circuit requires countermeasures!
An error is not a problem as long as it does not affect the logic.
It would be convenient to have a feature that allows us to verify that there are no problems using formal verification or logic simulation.

* If you are interested in Questa CDC, please contact our sales representative or use the Siemens EDA product inquiry form.