Narrow down by specifying conditions
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In this column, we will introduce "technical information on FPGA that is surprisingly unknown, but makes a difference if you know it."
From FPGA beginners to veterans, the contents can be used widely, so please keep in touch with us until the end.
[Part 2] Verification methods not recommended for designs that have already been commercialized
A certain company decided to share a lot of design data created by each department in the company as an internal IP.
However, we found bugs in some proven IPs that are already in mass production.
Functionality was verified by logic simulation, and further verification was performed on the actual machine at the system level, and there were no problems with mass-produced products.
When the same IP is used in applications with different uses, problems occur due to usage that the IP designer did not assume.
ABV (Assertion Based Verification)
Therefore, ABV (assertion-based verification) was introduced as a countermeasure.
If you use a randomly generated test bench using ABV, you can verify "unexpected behavior",
It increases the chances of discovering bugs that the designer would not have noticed.
When I ran ABV on other IPs that have already been proven in mass production, I also found multiple bugs.
Recent designs have deep layers, so it is difficult to find bugs in the front part of the circuit even if you verify it on an actual machine.
(Because the erroneous signal is slow to reach the output pin).
By combining ABV and logic simulation, design quality can be improved.
● ABV is effective in finding bugs in the front stage of the circuit
● Logic simulation is effective in finding bugs in the latter part of the circuit.
Click here for details of ABV
https://www.macnica.co.jp/business/semiconductor/articles/siemens/2122/