SoC FPGA Bare Metal All-in-One Application Samples - Semiconductor Business -Macnica

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DesignFPGA /CPLD/ASIC Microcomputer/Processor/DSP Intel

[Notice]Sample projects have been updated for the latest tool environment "Intel® Quartus Prime Standard Edition Development Software v22.1, Arm® Development Studio (Arm DS) 2022.2". (2023.03.23)

This sample can be used as a starting point for building bare-metal applications for Intel® SoC FPGAs.

Since the code necessary for bare metal development such as the hardware library (hereinafter referred to as HWLib) is placed in the project in advance and targeted for build, the user can simply include the necessary header files without editing the Makefile. It is possible to use the API.

Also, unused APIs are excluded when linking, so they do not affect the code size.

The attached document explains:

Usage environment (supported version, supported board)
Advantages of using this sample
Sample directory/file structure
Compile settings
Basic operation of the sample
How to add commands
Description of the main routine source code of this sample
Introduction to useful utility functions
What is HWLib (Hardware Library)?
HWLib Examples

Advantages of using this sample

A normal baremetal sample application is configured to use only the HWLib for the corresponding interface, and to use other HWLibs, you need to modify the Makefile and specify additional HWLib sources. .

In addition, since it is provided in the Makefile project, it is necessary to add the source files added by the user to the Makefile, and it takes time to understand for those who are not familiar with the software development flow of Intel® SoC FPGA. was.

In this sample, all sources provided as HWLib have been registered, and all APIs can be used by including the HWLib header files you want to use.

In addition, all source files added to the TOP directory of the project are set to be compiled, so basically you can start various evaluations without modifying the Makefile.

usage environment

This section describes the development environment and compatible target boards. For more detailed information, please refer to the attached instructional material (.pdf).

Development environment

The main development environments used in the explanations in the attachments are shown below. This sample project uses the following environment to check the operation.

[Table 1] Main environments used in the explanations in the attachments

item number	item	Latest version (Ver22.1 / for Arm DS)	Old version (for Ver18.1 / DS-5)
1	Host PC	64 bit machine with Microsoft ^® Windows ^® 10 (64 bit)	64 bit machine with Microsoft ^® Windows ^® 7 Professional SP1 (64 bit)
2	Intel® Quartus® Prime Standard Edition Development Software (hereafter referred to as Quartus Prime) * A tool for developing SoC FPGA hardware.	Use ^Intel® ^Quartus® Prime Standard Edition development software v22.1. Quartus® Prime Standard Edition v22.1 Reference: For information on how to install Quartus ^® Prime, refer to the following site. Quartus® Prime & ModelSim® InstallationNote: It is necessary to install the Device data corresponding to the SoC FPGA mounted on the target board to be used. Note:This document only uses the Quartus ^® Prime Programmer to download the hardware design (.sof file) to the FPGA in "4-6. FPGA Configuration".	Use ^Intel® ^Quartus® Prime Software Standard Edition v18.1. Quartus® Prime Standard Edition v18.1 Reference: For information on how to install Quartus ^® Prime, refer to the following site. Quartus® Prime & ModelSim® Installation Instructions (v18.x) Note: It is necessary to install the Device data corresponding to the SoC FPGA mounted on the target board to be used. Note: In this document, only Quartus ^® Prime Programmer is used to download the hardware design (.sof file) to FPGA in "4-6. Configuring FPGA".
3	Arm® Development Studio Intel® SoC FPGA Edition (Arm DS) / Intel® SoC FPGA Embedded Development Suite Standard Edition (SoC EDS) * A tool for developing software for SoC FPGA.	Point: This version of the sample project can be used without installing SoC EDS. (See attachment for details) Arm DS must be installed separately from SoC EDS. Arm DS allows you to compile and debug your application software. If you use SoC EDS Standard Edition v20.1, get it from: SoC EDS Standard Edition v20.1 Reference: For information on how to install SoC EDS and Arm DS, please refer to the following sites. How to install SoC EDS ver.20.1 Note: Debugging bare-metal applications using ^Intel® FPGA Download Cable II (hereafter referred to as USB-Blaster™ II) requires Arm DS/DS-5 (paid version).	Arm ^® Development Studio 5 Intel ^® SoC FPGA Edition (DS-5) included in SoC EDS can be used to compile and debug application software. Use SoC EDS Standard Edition v18.1. SoC EDS Standard Edition v18.1 Reference: Please refer to the following site for how to install SoC EDS. How to install SoC EDS ver.18.1 Note: DS-5 (paid version) is required for debugging bare metal applications using the ^Intel® FPGA Download Cable II (hereafter referred to as USB-Blaster™ II).
4	Terminal emulation software	A serial terminal software is required to use this sample. This article uses freeware software called "Tera Term". Tera Term download URL Notes: In Tera Term, please make the following settings for the valid COM port when connecting to the UART of the target board. ・ Baud rate 115200 bps ・ 8-bit data ・ No parity ・ 1 stop bit ・ No flow control	same as left

Compatible target board

In this sample, the following target boards can be specified by TARGET_BOARD in the config.mk file.

[Table 2] Supported target boards for this sample

item number	target board
1	Cyclone® V SoC Development Kit
2	Intel® Arria® 10 SoC Development Kit
3	Helio - Cyclone® V SoC Kit (Discontinued)
4	Sodia - Cyclone® V ST SoC Evaluation Board (Discontinued)
5	DE0-Nano-SoC Kit / Atlas-SoC Kit (Discontinued)
6	DE10-Nano Kit

Supplement and Notes

・ This sample project can be used in a Linux OS environment in addition to the Windows® environment listed in [Table 1] for the host PC.

・ The sample project of the latest version (for Ver22.1) does not include data for the Helio board. If you want to use it with Helio, please use the old version (for Ver18.1) sample project.

- The latest version (for Ver22.1) sample projects can also be used with older versions (Ver19.1 or later) that use Arm DS. In that case, please use the latest version (2022.2) for Arm DS.