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This "Self-study Intel® FPGA OpenCL Basic Exercises" series is a material that explains how to perform high-level synthesis of FPGA logic using the Intel® FPGA SDK for OpenCL using an Intel® SoC FPGA.
explanation
Experience a hands-on exercise using the FPGA SDK for OpenCL provided by Intel to understand how to quickly and easily build a hardware accelerator. The exercise implements a simple array addition process in OpenCL.
Documentation / Sample data
Self-study Altera OpenCL basic exercise (Atlas-SoC board edition)
Tool version: Document for Ver.15.1
Tool version: Practice data for Ver.15.1