Quartus® Guide - Assignment Editor - Semiconductor Business -Macnica

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DesignFPGA /CPLD/ASIC Altera Corporation

This "Quartus® Guide" series is intended for users of Quartus® Prime / Quartus® II development software.

For information on FPGA/CPLD development flows, please refer to this link.

explanation

This document will be useful during the "5. Setting Constraints" phase of FPGA/CPLD development.

This document describes how to apply individual constraints to individual nodes and entities in Quartus® Prime / Quartus® II development software.

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The Assignment Editor is a spreadsheet in Quartus® Prime/Quartus® II development software that allows users to set specific settings and constraints on pins and entities of circuits they have designed within a project. Various settings, such as options for enabling device-specific functions, pin assignments (*1), and I/O standard specifications, can be made on a single spreadsheet, enabling efficient and speedy operation. This document introduces the basic operations (*2).

(*1)
While pin assignments and I/O specification settings can be performed using the Assignment Editor, it is recommended to use the Pin Planner. For more information about the Pin Planner, please refer to "Quartus® Prime Pin Assignment".

(*2)
For users who want to learn about commonly used options in Altera® FPGAs, please refer to "How to Configure Commonly Used Pin Options in Quartus® Prime".