Quartus® Beginner's Guide - Pin Assignment Method - Semiconductor Business -Macnica

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DesignFPGA /CPLD/ASIC Altera Corporation

This "Quartus® Getting Started Guide" series is intended for users who are using Quartus® Prime / Quartus® II development software for the first time.

For information on FPGA/CPLD development flows, please refer to this link.

explanation

This document will be useful during the "5. Setting Constraints" phase of FPGA/CPLD development.

This document describes how to configure the target FPGA/CPLD pins using the Pin Planner in Quartus® Prime/Quartus® II development software.

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This document introduces how to assign user circuit pins to target device pin numbers using the Pin Planner in the Quartus® Prime / Quartus® II development software. It also guides you on how to set the pin's I/O standard and how to set the attributes of unused user I/O pins to individual pins (individual settings).

In addition, information on pin assignment is introduced, such as how to check the compilation report and the ability to check the compatibility of constraints after pin assignment. Please refer to this when making pin assignments.