Pin connection guidelines

Pin connection guidelines

Schematic Review Worksheet Top Page

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● Establish a measurement point near the FPGA

・Be ready to measure the power supply in case of trouble

・Refer to Power & Thermal Design & Debugging Guidelines​

● If all transceivers, fPLLs, and IOPLLs on the same side are unused,

・VCCR_GXB and VCCT_GXB can be connected to GND

・VCCH_GXBR can be connected to GND (Check pin connection guidelines for details)

● Decoupling capacitor

・Estimate with reference to the PDN tool​

・For a more detailed estimate, use a dedicated tool

<Reference>

　　Power Delivery Network (PDN) Analysis Tool

　　Part 9 Confirmation and Review of Capacity in FPGA Power Supply Design

● Power sequence

For more information, please refer to this document (Power Sequencing Considerations for Altera® Arria 10 Devices).

MSEL Pin Settings

Inserting pull-up/pull-down resistors⁽¹⁾⁽²⁾

Arria 10

* Refer to "MSEL Pin Settings" on the link

unnecessary

(see linked documentation)

● DCLK

・Recommend inserting damping resistor (minimum 0Ω) 10-50Ω

・In AS mode, take care of the trace length (see the document below)

　　Trace Length Guideline (from "Configuration, Design Security, and Remote SystemUpgrades in Altera®l Arria 10 Devices")

● nCONFIG, nSTATUS

・Pull up to VCCPGM via 10kΩ resistor

● CONF_DONE

・Pull up to VCCPGM via 10kΩ resistor

・Do not connect to the LED as it is.

- Due to lack of drive current, it may not light up without applying FET

● CLKUSR

・When using a transceiver or HMC (Hybrid Memory Cube)

- use CLKUSR as their calibration clock (required)

- must be entered before configuration

- For AS mode, input 100MHz clock

- For PS, FPP mode, input 100 ~ 125MHz clock

● For migrating from EPCS/EPCQ to EPCQ-A, refer to AN822: Altera® FPGA Configuration Device Migration Guideline.​

● When FPGAs are cascaded, nSTATUS and CONF_DONE are pulled up in common.

● nCE

・Connect to GND for single device configuration.

・This signal determines whether the FPGA is cascaded.

● When using nCEO, pull up to VCCPGM through a 10kΩ resistor.

● Check Point

・It is recommended to insert a 0Ω damping resistor for TCK.

- To support cases where writing is not possible due to problems with the clock system

● Pin processing

・TCK: pull down via 1kΩ resistor

・TDI: Pulled up to VCCPGM via 1kΩ to 10kΩ resistor

・TMS: Pulled up to VCCPGM via 1kΩ to 10kΩ resistor

・TDO : No pull-up/pull-down

・TRST : Option used. Pull up to VCCPGM through a 1 kΩ resistor if unused.

● When using a single-ended clock, assign it to the p-channel

(Does not ride on global clock directly on n-channel. Limitation when using ALTCLKCTRL buffer)

● Connect clock input pins that are not shared with I/O pins to GND if they are not used.

● Pay attention to AC/DC coupling when inputting differentially.

● If you are using a PLL, pull down the RREF pin through a 2kΩ resistor (resistor accuracy is ±1%).

● CLK and PLL pins can be left unconnected if not used.

pin name

comment

Pulled down through a 2kΩ±1% resistor

TEMPDIODEp/n

● When not using the transceiver

・Clocks (REFCLK_GXB*_CHp/n) are individually connected to GND or collectively pulled down via a 10kΩ resistor.

・RX (GXB*_RX_*p/n) is connected to GND

・TX (GXB*_TX_CHp/n) is floating

● AC/DC coupling

・Adjust to I/O Standard

Cyclone V SoC Pin Names

comment

BOOTSEL[2:0]

Pulled up or down to VCCIO voltage through a 4.7kΩ resistor

HPS_nRST (bidirectional pin)

Pulled up to VCCIO_HPS voltage through a 1kΩ resistor

SDMMC

Pulled up through a 10kΩ resistor

● Connect to GND if not used as a function pin and not used as a user I/O pin.

・ CLKUSR

・ DEV_OE

・DEV_CLRn

・PR_REQUEST