How to lower Idc

(a) Maintaining a logic state in which DC power does not flow
3rd time column, the pull-up/down buffer keeps the logic state in which no DC current flows for a long time.

(b) avoid signal conflicts
If the signals of the bi-directional buffer conflict (the L signal and the H signal collide), Vcc and GND are connected, so a large amount of power is consumed.
Avoid conflicts or keep conflict times short.

(c) Increase the pull-up/down buffer resistance
Increasing the resistor value flattens the waveform, but reduces the current through the resistor.

(d) Utilization of power-down mode
Blocks that support power-down mode frequently enter power-down mode when they do not need to operate.

How to lower Ileak

The most effective ways to reduce leakage are to increase the Vt (threshold voltage) and to implement power gating.
Altera supports both of these low-power methods.

(a) Methods to increase Vt (threshold voltage)
Vt (threshold voltage) is the voltage that acts as a dividing line to distinguish between Low and High in logic.
For example, raising the threshold height makes it more difficult for electric charges to overcome the threshold, thus reducing leakage current. However, it also makes it more difficult for normally operating charges to overcome the threshold, resulting in a decrease in speed.
As you can see, increasing Vt significantly reduces leakage current, but it has the drawback of slowing down the speed. It's similar to a hurdle race.

Altera's "Programmable Power Technology" allows ^Quartus® Prime to automatically lower Vt for critical paths to increase speed and increase Vt for other paths to reduce power consumption.
This is a highly effective technique because the critical path portion of the entire circuit is small.

In the future, as the timing accuracy of Quartus Prime improves and the range of Vt increase becomes larger, and as Vt can be dynamically controlled, its effectiveness will increase even further, making it a promising low-power technology for the future.

Competing FPGA vendors are evaluating this programmable power technology solely on dynamic power and claiming it's ineffective, but please note that this technology primarily reduces leakage power.

(b) Power Gating
Power gating is a function that cuts off the power supply to circuits that are not in use.
Altera has begun supporting power gating in its DSPs and memory cells.

In the future, if dynamic power gating for the logic portion becomes possible, leakage power can be significantly reduced, making this a promising low-power technology.

(c) Small chip area
To reduce chip area, there are two methods: making the circuit smaller and using miniaturized processes.
Miniaturized FPGAs have high leakage power, but the larger circuit size allows for a smaller chip area.
The increased power consumption when using the latest FPGA processes is due to the increased circuit size and speed.
The power consumption figures published by FPGA vendors appear low because they are compared under the same circuit size and speed.

(d) Partial reconfiguration
Partial reconfiguration is a function that changes the circuit configuration of some blocks while the system is running.
By turning off unused circuits, you can reduce the leakage power associated with those circuits.

(e) Lower the temperature
The subthreshold leakage current, which is currently the subject of concern, is highly temperature-dependent, and it is said that its value can increase tenfold for every 50°C increase in temperature.
Reducing dynamic power, or lowering the chip temperature by considering cooling methods and board layout, will reduce leakage power.
Siemens EDA HyperLynx Thermal While this method doesn't allow for precise thermal analysis of the circuit board, it's recommended because it's inexpensive and easy for anyone to use to distribute the heat generated by the FPGA.

(f) Lower Vcc
7th However, the method I introduced also lowers leakage power because it lowers Vcc.
-SmartVID
"SmartVID" reduces leakage power by lowering Vcc.
-VCC PowerManager
The "VCC PowerManager" lowers Vcc, thus reducing leakage power.

(g) Low static power device grade
Altera offers "low-static power device grade" FPGAs that consume less static power than standard power-hungry devices while maintaining performance.
By simply adopting this device, you can reduce leakage power.