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This "Quartus® Guide" series is intended for users of Altera® Quartus® Prime development software.
For information on FPGA/CPLD development flows, please refer to this link.
explanation
This document will be useful during the "6. Compilation" phase of FPGA/CPLD development.
Design Space Explore II (DSE II) is a tool that automates the process of performing multiple compilations while changing Quartus® Prime optimization settings. DSE II enables efficient design optimization.
This document introduces the settings for running DSE II and how to check reports after running.
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Altera® FPGA Development Flow / FPGA Top Page