This development support tool is equipped with a wealth of useful functions for RTL designers. It not only shortens the time required to create RTL and specifications, but also enhances design visibility, making it ideal for block reuse and team design.
▶ Introduction video
▶ Introduction of functions (HDL generation / HDL visualization / HDL code quality verification / version control)
▶ Related information
▶ Seminar/Workshop
▶ inquiry
Introduction video
Graphical View Transformation Tutorial
HDL Designer has various useful functions related to HDL language design. Among them, we will introduce the graphical view transformation, which is useful for documenting documents for efficient code understanding during reuse.
Implementing the DesignChecker function
HDL Designer has various convenient functions related to HDL language design. Among them, we will introduce DesignChecker, a lint check tool that can be used to uniform RTL design and improve design quality.
HDL Designer ~ RTL Simulator Linkage ~
Introduces the flow of linking with the RTL simulator on HDL Designer.
Feature introduction
The HDL Designer series has two types of tools. See below for a feature comparison.
・ HDL Designer
・ HDL Authors
HDL code quality verification
The lint check function (DesigneChecker) is static verification, so it doesn't take as long as simulation. You don't even need a testbench because you just apply the standard rules.
Related information
▶ How to download the Siemens EDA tool
▶ How to install HDL Designer
▶ How to license Siemens EDA tools
Seminar/Workshop
▶ [Online Seminar] Efficiency with HDL Designer! Improving the quality of FPGA design and utilizing design assets <Free>
We will introduce how to use tools to raise the quality of HDL design, improve the overall design quality, and how to reduce development man-hours by efficiently reusing design assets (existing designs).
▶ Events and seminars related to Siemens EDA
Inquiry
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