HDL Development Support Tool / HDL Designer

Click here for product descriptions, quotations, demos, evaluation requests, etc.

Click here to apply for a seminar on this product

This development support tool is equipped with a wealth of useful functions for RTL designers. It not only shortens the time required to create RTL and specifications, but also enhances design visibility, making it ideal for block reuse and team design.

Introduction video
Introduction of functions (HDL generation / HDL visualization / HDL code quality verification / version control)
Related information
Seminar/Workshop
inquiry

Introduction video

Graphical View Transformation Tutorial

HDL Designer has various useful functions related to HDL language design. Among them, we will introduce the graphical view transformation, which is useful for documenting documents for efficient code understanding during reuse.

Implementing the DesignChecker function

HDL Designer has various convenient functions related to HDL language design. Among them, we will introduce DesignChecker, a lint check tool that can be used to uniform RTL design and improve design quality.

HDL Designer ~ RTL Simulator Linkage ~

Introduces the flow of linking with the RTL simulator on HDL Designer.

Feature introduction

The HDL Designer series has two types of tools. See below for a feature comparison.

・ HDL Designer
・ HDL Authors

HDL Designer Series Comparison (Version: 2021.4)

HDL generation

Quickly generate HDL from block diagrams, state machines, truth tables and flowcharts.

HDL visualization

Code visualization is a shortcut to a better understanding of your design. Source files can be converted into graphic representations such as block diagrams, flowcharts, and state machines.

HDL code quality verification

The lint check function (DesigneChecker) is static verification, so it doesn't take as long as simulation. You don't even need a testbench because you just apply the standard rules.

version control

Multi-access control is essential in a team design environment. In an environment where multiple designers share a design database, it is necessary to constantly monitor data access status to prevent simultaneous modifications and careless rewriting of designs.

Related information

How to download the Siemens EDA tool
How to install HDL Designer
How to license Siemens EDA tools

Seminar/Workshop

[Online Seminar] Efficiency with HDL Designer! Improving the quality of FPGA design and utilizing design assets <Free>

We will introduce how to use tools to raise the quality of HDL design, improve the overall design quality, and how to reduce development man-hours by efficiently reusing design assets (existing designs).

Events and seminars related to Siemens EDA

Inquiry

Manufacturer information Top

If you would like to return to the manufacturer information top page, please click below.



Trademarks and registered trademarks owned by Siemens: here