Low ON-resistance SiC FET that can reduce overall loss

Qorvo offers a very distinctive cascoded SiC FET. A simplified schematic of the internals of the actual device is shown in Figure 1. As you can see, the SiC-JFET and Si-MOSFET are cascode-connected. This type of connection makes it appear as if Si-MOSFETs are connected to the user, greatly improving usability.

In addition, SiC-JFET is called normally-on, and when the gate, etc. is opened, it turns ON and enters a dangerous mode. Only Qorvo is currently developing such SiC.

Reasons why Qorvo's SiC FET devices have low on-resistance per unit area

Figure 2 shows a simple cross-sectional structure of a general SiC MOSFET and Qorvo 's cascode-connected SiC FET. We will analyze the on-resistance when voltage is applied, but the parameters R_Drift and R_JFET are almost the same for both SiC MOSFET and SiC JFET. However, SiC MOSFETs have a channel resistance that is extremely high. Compared to the value of Qorvo 's Si MOSFET, the value of a general SiC MOSFET is about 10 times worse. For example, when 650 V is applied, the channel resistance accounts for more than 50% of the total on-resistance.

Looking at Qorvo's SiC FETs, JFETs do not have channel resistance like SiC MOSFETs, but they do have the on-resistance of Si MOSFETs. This Si MOSFET is uniquely designed by Qorvo and has a very low on-resistance. This results in a value less than 10% of the overall FET on-resistance, resulting in a lower total on-resistance.

Qorvo 's latest generation 750V Gen 4 series now offers more design margin for 400V or 500V battery / bus voltage applications than its predecessor. Gen4 devices employ advanced cell densities, even with increased voltage ratings, enabling lower RDS (on) per unit area and the lowest on-resistance products in the industry provided in all packages.

Additionally, high current ratings are achieved through advanced sintered die attach technology, providing improved heat dissipation performance. Figure 3 compares the on-resistance per unit area of the new 750V product to a competitor's 650V rated product. It shows significantly lower values over the entire temperature range.

Qorvo has expanded its groundbreaking Gen 4 SiC FET portfolio to include 750V/6mΩ SiC FETs in TO-247 4-lead packages and up to 9mΩ on-resistance in D2PAK-7L surface mount packages. See Figure 4.

Leveraging the industry's highest on-resistance x area (RDS(on) x A), Qorvo expands its Gen 4​ ​FET portfolio across a wide range of power levels and package options to deliver best-in-class figures of merit. 750V SiC FETs in TO-247-3L and TO-247-4L through-hole packages with 6mΩ to 60mΩ on resistance and 9mΩ to 60mΩ in low inductance surface mount D2PAK 7L package with 6.7mm creepage for high voltage provided by

Figure 5 shows the extended 750V portfolio with eight on-resistances in both through-hole and surface mount devices. This allows designers to optimize their systems for efficiency, thermal management complexity, and cost without compromising on limited options.

Also, with a complete selection of 750V devices, designers can use the same benchmark technology provided by Qorvo to design many applications and power levels. Low on-resistance options are offered in Kelvin source connection packages (TO-247-4L and TO-263 7L), allowing users to achieve faster high current switching with cleaner gate waveforms.

Meanwhile, low-power SiC FETs (18mΩ to 60mΩ) are offered with Kelvin connections and traditional TO-247-3L options.

In addition, we are expanding our product portfolio of surface mount type TO leadless (TOLL) packages with Gen 4 SiC FETs.

See below for more information on TOLL packaged products.

Positive temperature coefficient of on-resistance for easy paralleling

A cascode SiC FET with a positive temperature coefficient of on-resistance means that it loses power at higher temperatures. When designing a system for high temperatures, it is necessary to pay attention to temperature rise and heat dissipation.

On the other hand, this positive temperature coefficient is an advantage when cascode SiC FETs are connected in parallel. When one of the multiple cascode SiC FETs connected in parallel heats up, the on-resistance of that device increases, resulting in a decrease in the current flowing through the device. Therefore, the power consumption is reduced, and it acts in the direction of equalizing the temperature.

Summary

Qorvo 's SiC FETs offer lower on-resistance products compared to other companies, enabling discrete rather than modular development for high power density applications. In addition, cost reduction is possible by replacing modules with discretes.

In addition, since it is a low ON resistance product, heat generation can be suppressed even when connected in parallel, making it easier to connect in parallel than other companies. Qorvo 's SiC FETs will be products that can meet high power density requirements.

Related information

• Key role of cascode in SiC success
• A very unique and easy-to-use cascode-connected "SiC-FET" series
• Using a cascode topology to defeat the Miller effect of solid-state switches
• Realization of highly efficient power conversion using SiC cascode
• How cascode connections ease the challenges of using SiC JFETs
• Cascoded Qorvo devices in high voltage PhaseShift full bridge
• Qorvo technical content list

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