1. FPGA and memory data transfer method - SDR and DDR -

As mentioned at the beginning, the data transfer method differs between the FPGA and memory and inside the FPGA.

Inside the FPGA, data is transferred using the SDR (Single-Data-Rate)method, which transfers data only at the rising edge of CLK.

On the other hand, data is transferred between FPGA and memory using the DDR (Double-Data-Rate)method, which transfers data at both the rising and falling edges of CLK.

FPGAInternal data transfer method: SDR (Single-Data-Rate)

FPGA- Data transfer method between memories: DDR (Double-Data-Rate)

*SDR and DDR have been explained in previous articles.

I have a question here.

“Even if data is transferred from the memory to the FPGA using the DDR method that allows data to be processed at the rising and falling edges of CLK,

Since the FPGA uses the SDR method that transfers data only at the rising edge of CLK, isn't it possible to process the data? 』

I asked my senior about it.

Wrinkles "Can data transferred from memory in DDR format be processed in SDR format FPGA?"

Senior: "FPGA can process in parallel, so it can be processed."

Although I should have learned it in training, I completely forgot that FPGA can perform parallel processing.

Then, how is the data transferred from memory by DDR method processed in FPGA?

2. Processing DDR data by FPGA

A diagram of DDR data processing by the FPGA (Figure 1) and data and clock timing diagrams (Figure 2) and abbreviations are shown below.

To allow data transferred in DDR to be processed in SDR

[1] First, phase shift CLK by 90° (CLK → Inclock).

[2] Next, if DATA_IN is taken at the rising edge of Inclock, the output will be DATA_OUT_1, and only data A will be output.

[3] If DATA_IN is taken at the rising edge of NOT_Inclock, the output will be similar to REG_OUT, and only data B will be output.

[4] Output by [3] REG_OUT of Inclock By taking the timing of the rise of DATA_OUT_1 (Data A) at the same time as DATA_OUT_2 (Data B.) is printed.

In this way, by using a 90° phase shift of CLK and NOT, and dividing the rising and falling data into two lines and processing them in parallel, the data transferred in the DDR method is converted into the SDR method and transferred to the FPGA. I found that it can process data successfully internally.

Using the knowledge of the data transfer method of FPGA and memory that I learned this time,

I would like to use it to respond to inquiries about timing analysis and timing design.

Summary

・ SDR (Single-Data-Rate) is a method that transfers data only at the rising edge of CLK.
​DDR (Double-Data-Rate) is a method that transfers data on both the rising and falling edges of CLK.

・Transfer data in SDR method inside FPGA, and transfer data in DDR method between FPGA and memory.

・Data transferred from memory in DDR format is converted to SDR format in the FPGA and processed in parallel.