DDR (Double Data rate)

This is the interface between DDR and FPGA. The memory controller inside the FPGA takes data on the rising and falling edges of the clock.

DATA in the figure below is 8 bits each.

DDR to SDR (Single Data Rate)

Inside the FPGA, data is passed to the user circuit in two stages. The first step is to convert double rate data to single rate.

Since data is acquired only at the rising edge of the clock, DDR → SDR transfers data in parallel.

Each data width is 8 bits, so the total data width is 16 bits.

SDR to HDR (Half Data Rate)

The data that has become single rate in the second stage will also become half rate. Like SDR, data is acquired at the rising edge of the clock, so data is transferred in parallel from SDR to HDR.

However, the difference from SDR is that the operating frequency is halved. By halving the operating frequency, the data width is also twice that of SDR and four times that of DDR.

Since each data width is 8 bits, the total data width is 32 bits.

Even if the operating frequency of HDR is halved, the data acquisition timing is the same as that of DDR by increasing the data width.

Changing DDR to HDR lowers the operating frequency and makes timing design easier.

* QDR clock frequency is 1/4 of DDR and SDR and data width is 8 times.