To make it an open-drain output:

1. Describe the behavior that results in an open-drain output in your design design.
   [Description example]
   • For Verilog-HDL
     assign A = OE? 1'b0 : 1'bZ;
   • For VHDL
     A <= '0' when OE = '1' else 'Z;
2. In that design, you set options in Quartus® to enable open-drain buffers on the device's I/O pins.
   
   1. Select Assignments menu ⇒ Settings
   2. Select Analysis & Synthesis (in Category)
   3. Check "Auto Open-Drain Pins" (default is "On")

* If you compile the Hi-Z output circuit without setting this option, Quartus® will implement it as a tri-state buffer.

In the Fitter compilation report, verify that the Open Drain section for the pin is marked "Yes."