Low ON-resistance SiC cascode JFET capable of reducing overall loss

ON Semiconductor offers a very distinctive cascode-connected SiC cascode JFET. A simplified circuit diagram of the inside of an actual device is shown in Figure 1. As you can see, the SiC-JFET and Si-MOSFET are cascode-connected. This type of connection makes it look like Si-MOSFETs are connected, which greatly improves usability.

In addition, SiC-JFETs are normally on, meaning that when the gate is open, they turn on and enter a dangerous mode, but by connecting them in a cascode, they can be made normally off. Only ON Semiconductor is currently developing such SiC cascode JFETs.

Why ON Semiconductor's SiC cascode JFET devices have low on-resistance per unit area

Figure 2 shows a simplified cross-sectional structure of a general SiC MOSFET and ON Semiconductor's cascode-connected SiC cascode JFET. We will analyze the on-resistance when voltage is applied, and the parameters R_Drift and R_JFET are almost the same for both SiC MOSFETs and SiC JFETs. However, SiC MOSFETs have something called channel resistance, which has a very high value. Compared to the value of ON Semiconductor's Si MOSFET, the general SiC MOSFET has a value about 10 times worse; for example, when 650V is applied, the channel resistance accounts for more than 50% of the total on-resistance.

Looking at ON Semiconductor's SiC cascode JFET, the JFET does not have the channel resistance of the SiC MOSFET, but it does have the on-resistance of a Si MOSFET. This Si MOSFET is designed by ON Semiconductor and has a very low on-resistance. This makes it 10% or less of the on-resistance of the entire FET, resulting in a low total on-resistance.

Figure 2: Differences in structure between standard SiC MOSFET and ON Semiconductor SiC cascode JFET

ON Semiconductor's latest generation 750V Gen 4 series provides more design margin for 400V or 500V battery / bus voltage applications than previous products. Despite the increased voltage rating, Gen4 devices employ advanced cell density, which allows for a reduction in RDS (on) per unit area, offering the industry's lowest on-resistance across all packages.

Additionally, the high current rating is achieved through advanced sintered die attach technology, providing improved thermal performance. Figure 3 compares the on-resistance per unit area of the new 750V product with a competitive 650V rated product, showing significantly lower values over the entire temperature range.

ON Semiconductor has expanded its groundbreaking Gen 4 SiC FET portfolio with a 750V/6mΩ SiC cascode JFET in a TO-247 4-lead package and up to 9mΩ on-resistance in a D2PAK-7L surface mount package. See Figure 4.

ON Semiconductor is expanding its Gen 4​ ​SiC cascode JFET portfolio across a wide range of power levels and package options, leveraging the industry's highest on-resistance x area (RDS(on) x A) to deliver best-in-class figures of merit. The 750V SiC cascode JFETs are available in​ ​TO-247-3L and TO-247-4L through-hole packages with on-resistances ranging from​ ​6mΩ to 60mΩ and in a low-inductance surface-mount D2PAK 7L package with 6.7mm creepage for high voltage capability.

Additionally, a full selection of 750V devices enables designers to address many applications and power levels using the same benchmark technology from ON Semiconductor, rather than designing with SiC components from multiple different manufacturers to cover a product range. Low on-resistance options are offered in Kelvin source connection packages (TO-247-4L and TO-263 7L), allowing users to achieve faster, higher current switching with cleaner gate waveforms.

Meanwhile, low-power SiC cascode JFETs (18mΩ to 60mΩ) are offered in Kelvin-connected and traditional TO-247-3L options.

Additionally, we are expanding our product portfolio with Gen 4 SiC cascode JFETs in surface mount TO-Leadless (TOLL) packages.

See below for more information on TOLL packaged products.

Positive temperature coefficient of on-resistance for easy paralleling

A cascode SiC FET with a positive temperature coefficient of on-resistance means that it loses power at higher temperatures. When designing a system for high temperatures, it is necessary to pay attention to temperature rise and heat dissipation.

On the other hand, this positive temperature coefficient is an advantage when cascode SiC FETs are connected in parallel. When one of the multiple cascode SiC FETs connected in parallel heats up, the on-resistance of that device increases, resulting in a decrease in the current flowing through the device. Therefore, the power consumption is reduced, and it acts in the direction of equalizing the temperature.

Summary

ON Semiconductor's SiC cascode JFETs offer lower ON resistance products than other companies, making it possible to develop discrete devices rather than modules for high power density applications. Replacing modules with discrete devices also enables cost reduction.

In addition, because it is a low ON resistance product, heat generation can be suppressed even when connected in parallel, making parallel connection easier than with other companies' products. ON Semiconductor's SiC cascode JFET is a product that can meet high power density requirements.

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