Narrow down by specifying conditions
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In this article, we will introduce the proper use of FPGA/ASSP in realizing the MIPI interface and specific examples.
The demand for MIPI interface is increasing mainly in camera products, consumer/industrial equipment, and recently in the automotive market.
I think that there are many people who get lost in the selection of IC especially when considering.
There are FPGA and ASSP as ICs that realize the MIPI interface.
In order to select the optimum IC, it is necessary to consider the merits and demerits of each and use them properly according to the situation.
I introduced this in my previous article, so if you haven't already, please take a look here.
In this article, we will introduce a wide variety of FPGA MIPI interface practical examples.
First of all, before that, I would like to touch on the proper use of FPGA and ASSP.
For example, ASSP is recommended if you want to "realize a single function specification that is not scheduled to change at a low cost" as shown in the figure below.
When ASSPs Are Considered
point
・I/F Bridge between SoC and CMOS sensor
・Cannot receive MIPI I/F on SoC
・Simple I/F only conversion does not require special processing in front of SoC
・Since sensors and SoC will continue to be used in the future, the I/F specifications will not change.
・There are no restrictions on board area or current consumption, so there is no problem even if you add a new ASSP.
・I want to realize the function at low cost
→ If you want to realize a single function that will not change for a long time at a low price, useASSP
In this way, you can take advantage of the advantages of ASSP in the case of "low-cost realization of single-function specifications that are not scheduled to change".
However, in the actual design,
Support for several types of sensors and displays, multiple I/F conversions, pre-processing, etc.
There are cases where ASSP cannot be realized and there are cases where FPGA is more advantageous.
Specifically, the cases are as follows.
〇 Can be realized only with FPGA / When there is merit from ASSP
・Do not want to change the board configuration or parts for each sensor or display (platform)
・Multiple I/F and want to perform pre-processing of data
・Since the I/F on the display side is special, it cannot be realized with ASSP. . .
In such cases, it will be necessary to consider specifications that take advantage of the flexibility and high-speed processing of FPGAs.
In addition to this, there are cases that can only be realized with FPGA,
There are a wide variety of cases where FPGA is more advantageous than ASSP.
Therefore, in order to realize the optimum MIPI interface, it is necessary to consider specifications not only for ASSPs but also for FPGAs.
From here, I will introduce an example of MIPI interface of FPGA.
Since there are so many to introduce, we have prepared a list below. Check out the cases that interest you.
Although the amount of information is rather large, only meaningful information is posted.
*Please contact our FAE for details.
FPGA MIPI interface example (case) list
|
Case |
detail |
keyword |
FPGA |
common occurrence |
| Display system | ||||
| DSI mode conversion | MIPI DSI to MIPI DSI | Change DSI Videp Mode, 4K Display, 2.5Gbps D-PHY | CrossLink-NX | ★★☆☆☆ (2.0) |
| Support for special LVDS I/F | MIPI DSI to LVDS | DSI, LVDS, DSP, Color Space Convertor | CrossLink/CrossLink-NX | ★★☆☆☆ (2.0) |
| Using multiple interfaces | LVDS to DP, MIPI CSI-2 | CSI-2, Low Power, Display Port | Certus-NX/CertusPro-NX | ★★★☆☆ (3.0) |
| Image signal processing/segmentation | MIPI DSI to LVDS | DSI, LVDS, 100K LUT, Scaling, Splitting | Certus-NX/CertusPro-NX | ★★★★☆ (4.0) |
| CMOS sensor system | ||||
| Multiple I/F & data pre-processing | MIPI CSI-2 to MIPI CSI-2 | CSI-2, data compression, 1.5Gbps D-PHY | CrossLink-NX | ★★☆☆☆ (2.0) |
| SLVS-EC to main IC | SLVS-EC to MIPI CSI-2 | CSI-2, SLVS-EC, MAX10Gbps SERDES, 100K LUT | CertusPro-NX | ★★★☆☆ (3.0) |
|
Platformization of parts/structures |
LVDS to MIPI CSI-2 | CSI-2, LVDS, Small Package 2.5mm square | CrossLink | ★★★★☆ (4.0) |
|
No available ASSP |
MIPI CSI-2 to LVDS | CSI-2, LVDS, 1.5Gbps D-PHY, 6K LUT | CrossLink | ★★★★★ (5.0) |
| others | ||||
| Use of own I/F | DDR LVDS to MIPI DSI | DSI, Original LVDS, 1.5 Gbps D-PHY | CrossLink/CrossLink-NX | ★★☆☆☆ (2.0) |
|
・Coordination of multiple sensors ・High-speed communication to the next stage |
MIPI CSI-2 to MIPI DSI | CSI-2, DSI, MAX 10Gbps Serdes, low power consumption | CertusPro-NX | ★★☆☆☆ (2.0) |
| Edge AI processing in front of SoC | MIPI CSI to Bus/I2C/SPI | CSI-2, AI | CrossLink-NX | ★★★☆☆ (3.0) |
Display system
Case: I want to consider a SoC/Display that only supports a specific DSI Video Mode
point
・I/F Bridge between SoC and Display
・When MIPI I/F in 4K class high band is required
・Mode conversion from Burst mode to Non burst sync pulse
→CrossLink-NXsupportsup to MIPIMAX 2.5 Gbps/lane ◎
Case: The LVDS I/F on the display side is special, so it cannot be handled by ASSP.
point
・Interface bridge between SoC and Display
・The format is different from RGB888 on the SoC side and YCbCr422 on the Display side.
→CrossLink-NXhas built-in DSP Block, so color space conversion is possible ◎
Case: Cannot be handled by ASSP because multiple I/Fs are used
point
・ There is no ASSP that can handle Display Port and MIPI I/F at the same time.
・There is a need for low power consumption, and it can be realized with lower power consumption than other companies.
→CertusPro-NXachieves100LUT medium scale logic and low power consumption◎
(1/4times lower power consumption than other companies)
Case: I want to process and divide the input signal and display it on each display
point
・I/F Bridge from USB Type-C to LVDS
・Various signal processing is required before inputting to the display
→ Advantages unique toFPGA that users can freely design
→In addition toI/F conversion, functions can be added withCertusPro-NXwith100K LUT ◎
CMOS sensor system
Case: I want to perform pre-processing of data with many interfaces
point
I want to receive high data rate MIPI I/F and perform data merge processing with low power consumption.
The above processing cannot be performed in ASSP, so we will consider it in FPGA
→CrossLink with2.5mmsquare,6K LUT,MIPI D-PHYsupporting MAX 1.5 Gbps ◎
Case: I want to receive the SLVS-EC output sensor with the main IC such as SoC
point
・I/F conversion between Image Sensor and Main IC
・It is necessary to handle SLVS-EC and MIPI I/F at the same time, and there is no ASSP
・Because it is a battery-powered product, low power consumption is required.
→MAX 10Gbps SERDES,CertusPro-NXfor 1.5/1.25 Gbps ◎
Case: I don't want to change the board configuration or parts for each sensor
point
・I/F conversion between Image Sensor and Main IC
・Since multiple image sensors are replaced on one board, the board configuration and parts change for each sensor with ASSP (I don't want to change)
・Needs for small packages that match the size of the housing
→ The electronic control circuit can be changed according to the sensor specifications.
Benefits unique toFPGA and minimum 2.5mmsquarepackage◎
Case: SoC I/F does not support MIPI and there is no ASSP that supports the format
point
・I/F Bridge between SoC and CMOS sensor
・The SoC cannot be accepted at MIPI
・There is no ASSP that supports RAW10 at full HD/60fps
→ForI/F conversion needs, the CrossLink series is ◎
Other cases
Case: ASSP cannot handle it because it uses its own I/F
instant on
・Interface bridge between SoCs
・Since the full-HD color depth is 10bit RGB444 and the frame rate is 120fps, the normal 7:1 LVDS is over the bandwidth, so it is necessary to build a unique LVDS I/F and bridge it to MIPI from there.
→ CustomizableoriginalI/F and CrossLinkspecialized forI/F conversion ◎
Case: I want to collect multiple image sensors and transfer them to a later stage using high-speed communication.
point
・I/F Bridge between main IC and sensor/display
・There is a need to reduce the board area, and ASSP requires multiple configurations.
It puts pressure on the board area.
・Low heat generation (low consumption) is required for products that come into contact with the human body.
→Minimum9mm x 9mm Package,10G SerDesrealized with low power consumption◎
Case: I want to add processing using edge AI to the front stage of SoC
point
・In addition to being used as a mere AI accelerator,
MIPI CSI2 I/F and AI engine can be implemented in one FPGA, and
Low power consumption and small size.
・In the case above, the FPGA functions as a sensor that uses AI, and by activating the Main SoC based on the inference results, it is possible to reduce the power consumption of the entire system.
・In the case below, it is possible to use the serial I/F that is often used as an I/F with the host.
→MIPI +edgeAIsolution for pre-processing of the mainIC in the latter stage ◎
Summary
In this article,
Proper use of FPGA/ASSP in MIPI interface
Examples of utilizing the flexibility and high-speed processing of FPGA
was introduced.
The advantages of FPGA came out again in the following cases.
・Need to support 2.5Gbps/lane MIPI DSI/CSI-2
・Need to support 10Gbps SERDES
・It is necessary to support special conversion and signal processing.
・There is a demand for low power consumption and low heat generation
・Need to save space
・There is a possibility that the need for circuit changes will occur, etc...
In order to realize the optimum MIPI interface, it is necessary to consider specifications not only for ASSPs but also for FPGAs.
If you have any questions, please feel free to contact our FAE.
New Engineer's Struggle ~MIPI Standard Version~
The MIPI standard is a communication standard often used in recent years for display interfaces and image sensor output interfaces.
I know the name of the standard, but what is the communication band? What protocol are you using? Such
Among MIPI, this article focuses on DSI/CSI for newcomers to study from scratch.
We are creating articles about the MIPI standard with the motto of making it easier to understand and more fun than other articles.
Would you like to study with a newcomer?