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This Quartus® Getting Started Guide series is for users who are new to the Intel® Quartus® Prime / Quartus® II development software.
See here for FPGA/CPLD development flow.
explanation
User I/O of FPGA / CPLD becomes unused user I/O if it is not logically used. The state of unused user I/O can be optionally selected according to board specifications. Describes how to set unused user I/O pins on the tool.
Document
Since v15.1, this document has been merged into "Quartus® Prime Pin Assignments" due to duplicate content.
"Getting Started with Quartus II - How to Handle Unused Device Pins" (Document for tool version: Ver.14.0)
Click here for recommended articles/materials
Quartus® Prime related articles and resources
Intel® FPGA Development Flow/FPGA Top Page
Click here for recommended FAQ
Click here for recommended seminars/workshops
Quartus® Prime Introductory Trial Course <Free>
Custom microcomputer design trial ~Experience embedded design using MAX® 10 FPGA! ~ <free>