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Metastability due to the connection of signals between different clock domains (CDC (Clock Domain Crossing)) is a problem in today's FPGA designs. Conventional structural verification alone is not effective for verifying CDC signals.
This column will be divided into four parts to explain the CDC problem and how to verify it.
Part 3: General measures against metastability and their problems
A general metastable countermeasure is to insert two or more stages of FFs in the receiving side clock domain in the latter stage, as shown in Figure 3-1. Recently, it has become common to insert three or more stages. A guideline for how many stages should be inserted can be found by checking the MTBF (Mean Time Between Failures) with the Quartus® II TimeQuest Timing Analyzer function. In addition, it is recommended to shorten the FF interval on the receiving side so as to shorten the metastable period.
Figure 3-1 General measures against metastability
If you insert several stages of FF, you can suppress the transmission of metastable to the later stages. But...the problem still remains. It's a matter of protocol and reconvergence.
protocol error
In the waveform in Figure 3-2, the 1st stage FF is metastable at the first clock, so the logic of the 1st stage FF output (Q1) is not stable. And since the second stage FF takes in the data (Q1) and sets the output (Q2) to Low (0), the metastable is not propagated to Q2.
However, the data changed after the second clock, so in this case we missed the first cycle data. This is a protocol error.
Even if metastability can be avoided, it is meaningless if data cannot be obtained. To prevent protocol errors, the data (D) must be stable until the 2nd stage FF can receive the data.
Figure 3-2 Protocol Error
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What if this is a Bus even if data is captured after it stabilizes so as not to cause a protocol error?
Bits that cause metastable are transferred in the next clock (2-cycle transfer), and other bits that do not cause metastable are transferred in the previous clock (1-cycle transfer).
The glitch caused by this is a reconvergence error.
Figure 3-3 Reconvergence
Do you have measures against reconvergence errors?
That's all for now. Next time, I will explain how to verify metastable.