Let's review the normal compilation flow first

The figure below shows the compilation flow normally performed by Quartus Prime.
The main process consists of the following four steps.

Of these, Analysis & Synthesis and Fitter (placement and routing) are the main tasks of the compiler.

In these two steps, the normal default compilation is to run “all designs” in the project.

Therefore, when recompilation is requested for the project, each module will be recompiled regardless of whether the design has been modified or the option settings have been changed.

why recompile

This situation can be a reason for users to recompile.

• Part of the design has changed (including addition/deletion of modules)
• Constraints have changed (pin layout, options, etc.)
• Couldn't meet the timing → To converge the timing

What concerns do users have about recompiling?

When you hear the word recompilation, most people probably have this image in mind.

"(Since it's a large-scale design, again) I don't want it to take a long time to compile."
"It's no good if the part where the timing is met collapses."

When recompiling, if you compile with the defaults without taking any precautions, all modules in the design will be re-synthesized and placed and routed. This means that modules that have not changed will also be compiled, and this “duplication of effort” will also consume time.

It also increases the possibility that the layout inside the device will change.

Even if the layout is changed, it is fine if the result satisfies the user's desired timing requirements, but there is also the risk that some blocks that were able to meet timing in the previous compilation will not be able to meet due to the layout change. can be

Quartus® Prime's Incremental Compilation eliminates that worry!

There is a method to recompile only the parts where the design or constraints have changed. That is "incremental compilation".
Only the designs that are added are compiled, reducing the time required to recompile existing designs.

Moreover, since the previous compilation (logic synthesis and placement and routing) information of the existing design is applied to the recompilation as it is, the netlist name changes each time the logic synthesis is performed, and timing is hit due to changes in the placement location. It is a technique that can reduce the risk of disappearance.

Let's take a look at an overview of this feature on the following page. (* Arria® 10 users, please see the next section.)

Try to use incremental compilation

Arria 10 features incremental optimization

For Arria 10, please use the "Incremental Optimization" feature provided by Quartus Prime Pro Edition. Please note that the names are very similar.

[Reference: Information on incremental optimization features]
Reducing the number of full design iterations through early placement stages (manufacturer's website)