explanation

This document will be helpful in the "3. Logic circuit design" phase of FPGA/CPLD development.

A simple introduction to how to use the Platform Designer (formerly Qsys) system integration tool.

* Qsys has been renamed to Platform Designer from v17.1.

The Platform Designer system integration tool provides interconnect logic (address/data bus connections, bus width matching logic, address decoder/ logic, arbitration logic, etc.) to save significant time and effort in the FPGA design process. Platform Designer is developed with new FPGA-optimized Network-on-Chip (NoC) technology and offers improved performance, ease of design reuse, and verification compared to the previous generation tool, SOPC Builder. speed up.

Recently, Platform Designer is often used to incorporate the Nios® II processor (hereafter referred to as Nios® II) or the ARM® core built into the FPGA device into the FPGA design. increase.

Document

ELS1425_Q1600_10__1.pdf

"Quartus Prime Guide - Using Qsys System Integration Tools ver.16" (Tool version: Ver 16.0 document)

Click here for recommended articles/materials

Articles and materials related to Quartus® Prime
IP-related articles and materials
Articles and materials related to Nios® II
Articles and materials related to SoC FPGAs
Altera® FPGA Development Flow / FPGA Top Page

Click here for recommended FAQ

Quartus® Prime related FAQs 
Altera® FPGA-related FAQs