Intel: I would like to check if the hard processor system SPI can be connected by loopback and can be sent and received correctly. Is it possible to output the SPI interface from the Hard Processor System (HPS) and connect it on Platform Designer like Conduit?

Intel: Is there a way to trigger Signal Tap at the same time when breaking on the Nios® II SBT for Eclipse?

Intel: The following warning appears for the DQ signal of SDRAM Controller Intel FPGA IP. How should I deal with this?

Intel: I have generated and implemented the Signal Tap Logic Analyzer with IP Catalog, can I deploy it to an STP file reflecting the settings?

Do MAX 10 devices support the SignalTap II Logic Analyzer?

In SignalTap II, Node finder doesn't detect the node even though it is visible in Viewer. Any ideas?

Intel: What is the TalkBack feature?

I compiled a project I created earlier with the latest Quartus II, but an error occurred and the compilation terminated. Please tell me how to resolve.

Intel: I compiled a project I created a while ago with the latest Quartus II, but the compilation terminated with an error. Please tell me how to resolve.

I want to change the internal signals monitored by SignalTap II.Do I need to compile?

Intel: Is it possible to debug Nios II behavior with SignalTap II?

How do I debug VIP (Video and Image Processing) Suite?

00h and 0Fh appear in VIP (Video and Image Processing Suite) packet type identification numbers. What do they mean?

There is a place to set the clock for sampling in SignalTap II, but can I use any clock in the design?

I heard that SignalTap II uses FPGA resources. Is it possible to check approximate resources before compiling?

In SignalTap II, can I OR a single trigger condition into a trigger?

JTAG pins may or may not be auto-assigned, what is the difference? (Pin name: altera_reserved_tdi/tms/tck/tdo)

What is the maximum number of channels that SignalTap II can monitor?

What is the maximum amount of data that can be confirmed in one channel with SignalTap II?

In the SignalTap II Logic Analyzer, I get an error when I monitor rx_in for Megafunction Name(s) : ALTLVDS_RX (LVDS Receiver macro). The FPGA is a Stratix IV.

Can I use SignalTap II with CPLD devices such as MAX II and MAX V?

If I have two FPGAs connected in the JTAG chain, is it possible for SignalTap II to see each FPGA waveform at the same time?

Is there a way to observe Calibration-related (local_cal_success, local_init_done) signals on the External Memory Interface with SignalTap II?

I have logic (entities) in my design that I don't remember using, what is this? Sld_hub: auto_hub

Is there a way to deal with the following error (Fatal Error)?